在本篇論文中，我們提出使用選擇性參考電壓設計的低功率消秏低成本的6位元類比數位轉換器(6-bit Analog to Digital Converter)。我們使用新提出的選擇性參考電壓技巧，使得不同解析度使用不同的比較器，使得比較器的輸出即為二進制邏輯碼控制開關，無需額外的編碼器。因為傳統的快閃式的類比數位轉換器在N-bits的解析度時，需要使用到2n - 1個比較器，使得它的功率消秏、面積、輸入電容也增加了2n - 1倍。然本篇提出的新ADC當解析度為n時，只需要n個比較器，可以大大的節省功率消秏及面積，而且輸入電容也會降為n倍，且仍然保有非常高的取樣率。

本篇論文所設計之類比數位轉換器採用台灣積體電路製造公司(TSMC) 0.18μm 1P6M CMOS製程來實現，且供應電壓為1.8V於解析度為6位元下，類比數位轉換擁有的操作電壓範圍為0.5V至1.1V，取樣率達256MHz，微分非線性誤差約為+0.46LSB~0.49LSB，積分非線性誤差約為+0.85LSB~ -0.05LSB，而FOM僅為0.26 pJ/Conv，且功率消秏僅達4.2 mW，適合低功率低消秏成本的消費性電子應用。

In this paper, we present a low-power low-cost 6-bits, ADC using selective reference voltage technique. Using selective reference voltage technique, the different bit uses different comparator can be achieved. Meanwhile, the outputs from comparators are a binary code which can be used for generating logic condition thereby controlling the switches. Because the conventional n bits flash ADC requires 2n - 1 comparators and its power, area and input capacitance are all proportional to 2n - 1. Whereas, the proposed n bits ADC needs only n comparators which can save more power and area, and its input capacitance are proportional to n only, and keep high speed.

Our proposed ADC is design by TSMC 1P6M 0.18μm process with 6-bits resolution, 1.8V power supply. The signal input range 0.5V~1.1V, sampling rate 256MS/s, DNL +0.46LSB~ -0.49LSB, INL +0.85LSB~ -0.05LSB. In addition, the FOM of the ADC is only 0.26 pJ/Conv and the power consumption is only 4.2mW.It is good for a low-power and low cost customer electronic application.

第一章 導論.....................................................1
第二章 選擇性參考電壓設計的類比數位轉換器............15
第三章 整體電路的設計......................................22
3-1 邏輯控制開關...........................................22
3-2 比較器電路.............................................25
第四章 整體電路layout.....................................28
4-1 比較器電路Post-sim模擬...............................29
4-2 輸出級Post-sim模擬....................................30
第五章 模擬結果..............................................31
第六章 結論與未來研究方向.................................38
6-1 結論.....................................................38
6-2 未來研究方向............................................40
參考文獻........................................................43
附錄A、Layout圖...............................................47
附錄B、投稿VLSI會議的論文(Submitted).................48

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