本論文包含兩個主題，第一個主題是採用改良式NMCF頻率補償技術之LDO線性穩壓器；第二個主題是適用於測量神經訊號之低雜訊放大器。以上兩者主要皆應用於神經訊號適用之全植入式系統整合單晶片。

本論文首先提到的低壓差(low drop-out, LDO)線性穩壓器，是加入一個名為modified NMCF (nested Miller compensation with feedforward Gm stage)的補償技術，使線性穩壓器不用外掛補償電容以及補償電容的等效串聯電阻。而這樣的補償方式也提供了足夠的相位邊際確保了閉迴路的穩定。這個電路在4 V到5 V的區間內，電源供應拒斥比為30 dB(電源供應頻率為 [200 Hz, 3 MHz]，負載為 [50

This thesis includes two research topics. The first topic is a linear LDO regulator. The second one is a low noise amplifier (LNA). Both of the circuits can be applied to a totally implantable micro-electrical neural interfacing SOC.

The linear LDO regulator is enhanced with a novel compensation technology, called modified NMCF (nested Miller compensation with feedforward Gm stage), resulting in that its performance is independent of the off-chip capacitor and its ESR (equivalent series resistor). The proposed compensation method ensures the stability of the feedback loop and the large enough phase margin of the LDO (low dropout) regulator. The power supply rejection ratio is 30 dB (operating at [200 Hz, 3 MHz] and a load of [50

目錄
摘要 i
Abstract ii
第一章 簡介 1
1.1 論文動機　 1
1.1.1 LDO線性穩壓器的研究動機　 3
1.1.2 低雜訊放大器的研究動機　 3
1.2 先前文獻探討　 4
1.2.1 LDO線性穩壓器　 4
1.2.2 低雜訊放大器　 5
1.3 論文大綱　 6
第二章 採用改良式NMCF頻率補償技術之LDO線性穩壓器 7
2.1 概論　 7
2.2 原理概述　 8
2.3 架構與原理說明　 8
2.3.1 傳輸元件的選用　 8
2.3.2 NMCF頻率補償技術　 10
2.4 晶片製作　 12
2.4.1 設計考量　 12
2.4.2 佈局說明　 13
2.4.3 架構比較　 13
2.5 電路模擬與量測　 15
2.5.1 佈局後模擬結果　 15
2.5.2 量測結果與分析討論　 15
第三章 適用於測量神經訊號之低雜訊放大器 21
3.1 概論　 21
3.2 原理概述　 22
3.3 架構與原理說明　 22
3.3.1 第二級低通濾波器之電路　 23
3.3.2 帶差溫度補償電流源電路　 24
3.3.3 第三級高通濾波器電路　 25
3.3.4 以適當偏壓MOSFET取代大電阻之方法　 27
3.3.5 第四級高通濾波器電路及輸出級　 28
3.4 晶片製作　 28
3.4.1 設計考量　 28
3.4.2 佈局說明　 29
3.4.3 架構比較　 29
3.5 電路模擬　 32
3.5.1 佈局後模擬結果　 32
3.5.2 量測結果與分析討論　 33

第四章 結論與成果 36
參考文獻 38



圖目錄
圖1.1 全植入式微電刺激及神經訊號量測系統　 2
圖1.2 傳統LDO線性穩壓器架構圖　 4
圖2.1 LDO線性穩壓器架構圖　 8
圖2.2 本論文LDO線性穩壓器架構圖　 10
圖2.3 本論文LDO線性穩壓器詳細電路圖　 12
圖2.4 LDO線性穩壓器之佈局圖　 13
圖2.5 PSRR在不同電容性負載之下的表現　 16
圖2.6 PSRR在不同電阻性負載之下的表現　 16
圖2.7 PSRR在不同溫度之下的表現　 17
圖2.8 相位邊際在25oC之下的表現　 17
圖2.9 相位邊際在75oC之下的表現　 18
圖2.10 LDO線性穩壓器輸入對輸出電壓的量測結果　 18
圖2.11 LDO線性穩壓器量測輸出電壓起振情形　 19
圖2.12 LDO線性穩壓器的晶片照像圖　 19
圖3.1 低雜訊放大器架構圖　 22
圖3.2 第二級低通濾波器之詳細電路圖　 23
圖3.3 帶差溫度補償電流源電路　 24
圖3.4 第三級高通濾波器電路　 26
圖3.5 MOS通道等效電阻　 27
圖3.6 MOS通道等效電阻的偏壓電路　 27
圖3.7 第四級高通濾波器電路及輸出級　 28
圖3.8 低雜訊放大器佈局圖　 30
圖3.9 佈局後模擬之頻率響應　 31
圖3.10 各角落上之CMRR　 32
圖3.11 各角落上之功率消耗　 32
圖3.12 低雜訊放大器的晶片照像圖　 34
圖3.13 一至三級之頻率響應量測結果　 35
























表目錄
表2.1 LDO線性穩壓器架構比較 15
表2.2 模擬結果與量測結果的差異 16
表3.1 低雜訊放大器之架構比較 30
表3.2 模擬結果與量測結果的差異 33

[1] Y. Jiang, and E. K. F. Lee, “A 1.2V bandgap reference
based on transimpedance amplifier,” 2000 Inter.
Symp. on Circuits and Systems (ISCAS’00), vol. IV,
pp. 261-264, May 2000.
[2] D. Jurisic, and G. S. Moschytz, “Low-noise active-
RC low-, high- and band-pass allpole filters using
impedance tapering,” 2000 IEEE Electrotechnical
Conference (MELECON 2000), vol. 2, pp. 591-594,
2004.
[3] T. Akin, K. Najafi, and R. M. Bradley, “A wireless
implantable multichannel digital neural recording system
for a micromachined sieve electrode,” 1998 IEEE
J. of Solid-State Circuits, vol. 33, no. 1, pp. 109-118,
Jan. 1998.
[4] B. Razavi, “Design of analog CMOS integrated circuits,”
New York: McGraw-Hill, 2002.
[5] J. Sacristan, and M. T. Oses, “Low noise amplifier
for recording ENG signals in implantable systems,”
2004 IEEE International Symposium on Circuits and
Systems (ISCAS 2004), vol. 4, pp. 33-36, May 2004.
[6] A. Uranga, N. Lago, X. Navarro, and N. Barniol, “A
low noise CMOS amplifier for ENG signals,” 2004
IEEE International Symposium on Circuits and Systems
(ISCAS 2004), vol. 4, pp. 21-24, May 2004.
38
39
[7] C.-C. Wang, Y.-H. Hsueh, Y.-T. Hsiao, U Fat Chio,
C.-C. Huang, and P.-L. Liu, “An implantable neural
interface micro-stimulator chip with external controllability,”
2004 The Fourth IEEE Asia-Pacific Conference
on Advanced System Integrated Circuits (APASIC’
2004), pp. 356-359, Aug. 2004.
[8] S. R .Zarabadi, F. Larsen, and M. Ismail, “A reconfigurable
op-amp/DDA CMOS amplifier architecture,”
1992 IEEE Trans. on Circuits and Systems I: Fundamental
Theory and Applications, vol. 39, no. 6, pp.
484-487, June 1992.
[9] R. R. Harrison, “A low-power, low-noise CMOS amplifier
for neural recording applications,” 2003 IEEE
J. of Solid-State Circuits, vol. 38, no. 6, pp. 958-965,
June 2003.
[10] G. Bontempo, T. Signorelli, and F. Pulvirenti, “Low
supply voltage, low quiescent current, ULDO linear
regulator,” 2001 IEEE Trans. on Circuits and Systems
I: Fundamental Theory and Applications, vol. 1,
no. 9, pp. 409-412, Sep 2001.
[11] S. Yuan and B. C. Kim, “Low dropout voltage regulator
for wireless applications,” 2002 IEEE Power
Electronics Specialists Conference, vol. 2, no. 7, pp.
421-424, June 2002.
[12] T. J. Barber, S. Ho, and P. Ferguson, “Multi-mode
CMOS low dropout voltage regulator for GSM handsets,”
2002 VLSI Circuits Digest of Technical Papers,
pp. 284-287, June 2002.
[13] S. Bourret, M. Sawan, and R. Plamondon,
“Programmable high-amplitude balanced stimulus
current-source for implantable microstimulators,”
1997 IEEE Medicine and Biology Society, vol. 5, pp.
1938-1941, Nov 1997.
[14] J. S. Walter, J. S. Wheeler, W. Cai, W. W. King,
“Evaluation of a suture electrode for direct bladder
stimulation in a lower motor neuron lesioned animal
mode,” 2002 IEEE Trans. on Rehabilitation Engineering,
vol. 7, no. 2, pp. 159-166, June 1999.
[15] T. J. Barber Jr., S. Ho, and P. Ferguson Jr., “Multimode
CMOS low dropout voltage regulator for GSM
handsets,” Symposium on VLSI Circuits Digest of
Technical Papers, 2002, pp. 284-287, June 2002.
[16] G. W. den Besten, and B. Nauta, “Embedded 5 Vto-
3.3 V voltage regulator for supplying digital IC’s
in 3.3 V CMOS technology,” IEEE J. of Solid-State
Circuits, vol. 33, no. 7, pp. 271-273, Oct. 2001.
[17] K. C. Kwok and P. K. T. Mok, “ Pole-zero tracking
frequency compensation for low dropout regulator,”
2002 IEEE Inter. Symp. on Circuits and Systems (ISCAS’
02), vol. 4, pp. 735-738, May 2002.
[18] C. Stanescu, “Buffer stage foe fast response LDO,”
2003 International Semiconductor Conference, vol. 2,
pp. 357-360, Sep. 2003.
[19] K. N. Leung, P. K. T. Mok, and W. H. Ki, “A novel
frequency compensation technique for low-voltage
low-dropout regulator,” 1999 Inter. Symp. on Circuits
and Systems (ISCAS’98), vol. 5, pp. 102-105,
May 1998.
[20] K. N. Leung, and P. K. T. Mok, “Analysis of
multistage amplifier-frequency compensation,” IEEE
Transactions on Circuits and Systems, vol. 8, no. 9,
pp. 1041-1056, Sep. 2001.
[21] C.-C. Wang, and C.-C. Huang, “A 38-dB stopband
attenuation and 120-dB CMRR small-area LNA for
neural signal sensing and recording,” Inter. Conf. on
Systems and Signals (ICSS’2005), pp. 137, CD-ROM
version, H-III, Apr. 2005.