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博碩士論文 etd-0705113-144753 詳細資訊
Title page for etd-0705113-144753
論文名稱
Title
具有埋藏氧化層的垂直式金氧半場效應電晶體
Study of Vertical MOSFET with Embedded Oxide
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
93
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2013-07-18
繳交日期
Date of Submission
2013-08-07
關鍵字
Keywords
無接面、短通道行為、單一增益頻率、埋藏氧化層、垂直式電晶體
Unity Gain Frequency, Junctionless, Embedded Oxide, Vertical MOSFET, Short Channel Behavior
統計
Statistics
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The thesis/dissertation has been browsed 5800 times, has been downloaded 1505 times.
中文摘要
本篇論文裡,我們提出了具有埋藏氧化層架構之垂直式電晶體。使用埋藏氧化層的方法,可有效改善傳統SOI基板串聯電阻過大而導致元件操作電流較小的問題,大幅提升元件整體操作效率。我們利用TCAD模擬此款垂直式電晶體基本電性和類比特性,可以發現,在次臨限擺幅、汲極導致能障高度下降值(DIBL)以及操作/截止電流比例(Ion / Ioff)上,具有埋藏氧化層的垂直式電晶體比無埋藏氧化層的矽基板垂直式電晶體各別改善了10.5 %、15.7 %和20.6 %。而閘極轉導轉換效率(Gm / Id)的表現上,有埋藏氧化層的垂直式電晶體比無埋藏氧化層的矽基板垂直式電晶體提升了14.6 %。根據研究成果顯示,適當使用埋藏氧化層的技術,可達到改善垂直式電晶體的短通道行為、提高操作穩定性以及提升元件操作效率等,垂直式電晶體電性優化之目的。
以外,為了突顯垂直式電晶體的性能,我們討論有接面及無接面電晶體的電性比較,根據電性模擬的結果發現,有接面垂直式電晶體的操作電流比無接面垂直式電晶體的操作電流高出58.1 %。在短通道行為的表現上,有接面電晶體比無接面電晶體擁有更佳的次臨限擺幅及DIBL值,分別改善了6.15 % 及12.8 %。另外,在閘極轉導(Gm)、Gm / Id及單一增益頻率(fT)的表現上,有接面電晶體也比無接面電晶體有更優秀的類比特性,各別提升了30.25 %、42 %以及28.4 %。經由初步的模擬結果,可以發現,無接面電晶體在元件基本電性及類比特性上,並沒有比有接面電晶體更優秀。此外,經由埋藏氧化層的方式進行優化,不論有接面或無接面架構之電晶體,在短通道特性行為上皆有改善趨勢。因此,在未來的CMOS微縮應用及性能提升上,有效使用埋藏氧化層技術結合有接面垂直式電晶體,會是可行的電性優化方案。
Abstract
In this thesis, we propose a junction vertical MOSFET with embedded oxide (EO JVFET) and an junctionless vertical MOSFET with embedded oxide (EO JLVFET). We find out that the EO can improve the series resistances and drive current compared with vertical SOI device. According to the numerical simulation, we can find out that the subthreshold swing, DIBL and on / off current ratio (Ion / Ioff) of the EO JVFET can be respectively improved 10.5 %, 15.7 % and 20.6 % compared with the junction vertical MOSFET with bulk silicon structure (Bulk JVFET). We also find out the Gm / Id of the EO JVFET can be improved 14.6 % compared with the Bulk JVFET. Therefore, it is believed that based on the design requirements, the optimizations can be readily implemented through EO design in a vertical transistor structure.
In addition, we focus on the electrical characteristics of the JVFET and JLVFET through computer simulations. According to the numerical simulation, we can find out that the drive current, subthreshold swing and DIBL of the JVFET can be respectively improved 58.1 %, 6.15 % and 12.8 % compared with the JLVFET. So the JVFET has better short channel behavior. We also find out the transconductance (Gm), Gm / Id and unity gain frequency (fT) of the JVFET can be respectively improved 30.25 %, 42 % and 28.4 % compared with the JLVFET. In other words, it is believed that based on the design requirements, the EO JVFET is still considered as a candidate for future CMOS scaling.
目次 Table of Contents
目錄
第一章 緒論 1
1.1 背景 1
1.2 動機 3
第二章 元件操作機制與原理 5
2.1 MOSFET之物理機制 5
2.1.1 MOS電容器操作區域之能帶圖 5
2.2 元件設計及架構 8
2.3 元件操作機制 9
2.4 有接面及無接面電晶體電流公式之說明 13
第三章 元件製程設計 14
3.1 Silvaco TCAD 模擬理想製程流程 14
3.2 具有埋藏氧化層之垂直式電晶體的實際製程 16
第四章 結果與討論 19
4.1 Atlas物理模組說明 19
4.2 Silvaco TCAD模擬軟體之元件模擬結果 21
4.2.1 埋藏式氧化層厚度及對通道距離之模擬 21
4.2.2 垂直式無接面電晶體微縮性之電性分析 25
4.2.3 具埋藏式氧化層的垂直式電晶體之電性探討 28
4.2.4 傳統矽基板、矽覆絕緣基板及埋藏氧化層之垂直式有接面電晶體電性比較。 41
4.2.5 傳統矽基板有接面垂直式電晶體及具有埋藏氧化層的無接面垂直式電晶體之電性比較。 49
4.2.6 具有埋藏氧化層之垂直式有接面電晶體源極端PN接面Overlap深淺對元件電性之影響及變化。 55
4.2.7 具埋藏氧化層之垂直式電晶體實作結果 60
第五章 結論與未來展望 67
5.1 結論 67
5.1.1 埋藏氧化層厚度和通道距離之模擬結果 67
5.1.2 垂直式無接面電晶體微縮性之電性分析結果 68
5.1.3 應用埋藏氧化層的垂直式電晶體之電性比較結果 68
5.1.4 垂直式有接面電晶體在不同基板型態下之電性分析結果 69
5.1.5 Bulk JVFET和EO JLVFET之電性分析結果。 69
5.1.6 源極端Overlap深度變化對元件電性影響之分析結果 70
5.1.7 實際製程之結果與討論 70
5.2 未來展望 71
參考文獻 72
個人著作 77
共同著作 78
A.附錄[33] 80
A.1 平帶電壓(Flat-Band Voltage, VFB) 80
A.2 臨限電壓(Threshold Voltage, VTH) 80
A.3 功函數差(Work Function) 81
參考文獻 References
參考文獻
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