非揮發式記憶體已經在現在生活中無所不在，消費性電子產品中處處可見，而Flash記憶體有著與既有製程相符的優點，但也有著存取速度過慢及尺寸微縮的極限，無法真正取代SRAM或是DRAM，導致電子產品發展受到局限，也促使次世代非揮發性記憶體研究。
本論文是對次世代非揮發性記憶體中最被看好的電阻式記憶體進行元件改善，利用內嵌二氧化矽層使得可控制氧離子含量增加，並且利用Pt/ZnO/TiN與Pt/ZnO/SiO2/ZnO/TiN元件比較，釐清內嵌二氧化矽層後造成傳導機制改變，透過改變崩潰電流，提高可控制氧離子數，改變此元件操作端，而自我形成互補式電阻切換記憶體特性(Complementary resistive switches, CRS)。也經由可靠度測試得知內嵌二氧化矽層後，使其元件特性提升。
於內嵌二氧化矽層中摻雜高氧化數的過渡金屬釓後，使得二氧化矽層中含氧量大幅提高，可控制元件極性方向，更可使其產生多層堆疊互補式切換特性(CRS)特性，避免潛行電流產生。
利用Pt/ZnO/Gd:SiO2/ZnO/TiN元件與使用原子層氣相沉積氧化鉿薄膜堆疊後，形成Pt/ZnO/Gd:SiO2/ZnO/HfO2/TiN元件，在大電場作用下，因阻絲於氧化鋅層作用，阻絲與氧化鋅層接近歐姆傳導，因此本元件由氧化鉿層主導傳導機制，可自我形成選擇器，使得大電場發生穿隧傳導機制，且在回掃電壓時電流有急遽下降的現象，將其結果應用於元件上後，成功使其元件on/off ratio上升，增加記憶窗口。

This paper is surrounded by silicon oxide layer embedment in switching layer in resistive random access memory (RRAM).
First use of multi-target magnetron sputtering system making silicon oxide films embedment in ZnO/TiN and covered Pt with top electrode. Materials analysis find that the structure have embedment silicon oxide layer. Through compare measurement in electrical with have embedment silicon oxide layer (Pt/ZnO/SiO2/ZnO/TiN) and single layer (Pt/ZnO/TiN). And further found that self-formed complementary resistive switching behavior induced by varying forming current compliance. The embedment silicon oxide layer can promote reliability of random access memory.
Then use multi-target magnetron sputtering system doped inner transition element (Gd) in silicon oxide films (Pt/ZnO/Gd:SiO2/ZnO/TiN). Through vary current compliance can find four type I-V curve. It’s presumably due to Gd’s outer space has higher orbital. And further found that asymmetric current compliance will change the resistance and polarity direction. In the phenomenon can emergence of complementary resistive switching (CRS) characteristics.
Use Plasma-Enhanced Atomic Layer Deposition System making Hafnium oxide films that pile up (Pt/ZnO/Gd:SiO2/ZnO/HfO2/TiN). Through measurement in electrical can find that use Current-Voltage Fitting and found that reset characteristics operation on tunneling in strong electric field. Different device cross reference to find that behavior is zinc oxide and hafnium oxide interface occur Tunneling. This device has self-formed Selector.

[ 論文審定書 + i ]
[ 論文公開授權書 + ii ]
[ 誌謝 + iii ]
[ 中文摘要 + iv ]
[ Abstract + v ]
[ 目錄 + vii
[ 圖目錄 + ix ]
[ 第一章 序論 + 1 ]
[ 1-1前言 + 1 ]
[ 1-2研究目的與動機 + 2 ]
[ 第二章 文獻回顧 + 3 ]
[ 2-1 記憶體發展及簡介 + 3 ]
[ 2-1-1鐵電式記憶體(FeRAM) + 3 ]
[ 2-1-2磁阻式記憶體(MRAM) + 4 ]
[ 2-1-3相變化記憶體(PCRAM) + 5 ]
[ 2-1-4電阻式記憶體(RRAM) + 6 ]
[ 2-2電阻式記憶體切換機制 + 9 ]
[ 2-2-1阻絲理論(Filament theory) + 9 ]
[ 2-2-2互補式電阻切換記憶體 (Complementary resistive switches, CRS) + 10 ]
[ 2-3絕緣體載子傳導機制 + 12 ]
[ 2-3-1歐姆傳導(Ohmic Conduction) + 13 ]
[ 2-3-2蕭基發射(Schottky emission) + 14 ]
[ 2-3-3普爾-法蘭克發射( Poole-Frenkel emission) + 15 ]
[ 2-3-4跳躍傳導(Hopping Conduction) + 16 ]
[ 2-3-5穿隧(Tunneling) + 17 ]
[ 第三章 實驗設備與原理 + 18 ]
[ 3-1多靶磁控濺鍍系統( Multi-Target Sputter) + 18 ]
[ 3-2 N&K薄膜特性分析儀(N & K analyzer) + 19 ]
[ 3-3 傅立葉轉換紅外光譜儀 (Fourier-Transform Infrared Spectrometer) + 19 ]
[ 3-4 X光光電子能譜儀(X-ray Photoelectron Spectroscopy) + 21 ]
[ 3-5電性量測系統 + 22 ]
[ 第四章內嵌二氧化矽層對元件特性影響比較 + 24 ]
[ 4-1 氧化鋅薄膜及氧化鋅內嵌二氧化矽薄膜電阻式記憶體製作流程 + 24 ]
[ 4-1-1氧化鋅薄膜備製 + 26 ]
[ 4-1-2 內嵌二氧化矽薄膜備製 + 26 ]
[ 4-1-3 白金上電極備製 + 27 ]
[ 4-2氧化鋅及二氧化矽薄膜材料分析 + 28 ]
[ 2004/2/1 + Mid-FTIR化學定性分析 ]
[ 2004/2/2 + XPS化學定量分析 ]
[ 4-3氧化鋅薄膜及氧化鋅內嵌二氧化矽薄膜元件電性分析比較 + 30 ]
[ 4-3-1氧化鋅薄膜元件I-V特性 + 30 ]
[ 4-3-2 氧化鋅薄膜元件電流傳導機制及模型建立 + 32 ]
[ 4-3-3氧化鋅內嵌氧化矽薄膜元件I-V特性及模型建立 + 33 ]
[ 4-3-4氧化鋅內嵌二氧化矽薄膜元件電流傳導機制及模型建立 + 33 ]
[ 4-4崩潰電流限流控制互補式電阻式記憶體傳導機制[33] + 35 ]
[ 4-4-1比較不同崩潰電流對氧化鋅內嵌二氧化矽層電阻式記憶體元件特性 + 35 ]
[ 4-4-2不同崩潰電流對氧化鋅內嵌二氧化矽層電阻式記憶體I-V特性之模型 + 36 ]
[ 4-5氧化鋅薄膜及氧化鋅內嵌二氧化矽薄膜元件可靠度比較 + 37 ]
[ 4-5-1元件穩定與可靠度比較 + 37 ]
[ 第五章 內嵌富氧二氧化矽元件互補式電阻式記憶體特性 + 40 ]
[ 5-1 氧化鋅薄膜及氧化鋅內嵌釓金屬摻雜二氧化矽薄膜電阻式記憶體製作流程 + 40 ]
[ 5-1-1氧化鋅薄膜備製 + 41 ]
[ 5-1-2 釓金屬摻雜二氧化矽薄膜備製 + 41 ]
[ 5-1-3 白金上電極備製 + 42 ]
[ 5-2釓金屬摻雜二氧化矽內嵌氧化鋅薄膜材料分析 + 43 ]
[ 5-2-1 Mid-FTIR化學定性分析 + 43 ]
[ 5-2-1 XPS化學定量分析 + 44 ]
[ 5-3釓金屬摻雜二氧化矽內嵌氧化鋅薄膜元件電性分析 + 46 ]
[ 5-3-1釓金屬摻雜二氧化矽內嵌氧化鋅薄膜元件I-V特性 + 46 ]
[ 5-3-2 釓金屬摻雜二氧化矽內嵌氧化鋅薄膜元件電流傳導機制及模型建立 + 48 ]
[ 第六章 原子層氣相沉積氧化鉿薄膜對元件特性影響 + 50 ]
[ 6-1 氧化鋅薄膜、氧化鋅內嵌釓金屬摻雜二氧化矽薄膜及原子層氣相沉積氧化鉿薄膜電阻式記憶體製作流程 + 50 ]
[ 6-2具有原子層氣相沉積氧化鉿薄膜之Pt/ZnO/Gd:SiO2/ZnO/HfO2/TiN元件電性分析 + 51 ]
[ 6-2-1元件I-V特性 + 51 ]
[ 6-3原子層氣相沉積氧化鉿薄膜之四層堆疊結構元件傳導機制比較及模型建立 + 54 ]
[ 6-3-1具有原子層氣相沉積氧化鉿薄膜之四層堆疊結構元件傳導機制比較 + 54 ]
[ 6-3-2具有原子層氣相沉積氧化鉿薄膜之四層推疊結構元件電流擬合機制分析及模型建立 + 55 ]
[ 第七章 結論 + 58 ]

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