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博碩士論文 etd-0706109-133656 詳細資訊
Title page for etd-0706109-133656
論文名稱
Title
使用Flying Adder架構之全數位頻率合成器與 低功率低延遲週期之二維旁通有號乘法器
All Digital Frequency Synthesizer Using Flying Adder Architecture and Low Power Low Latency 2-dimensional Bypassing Signed Multiplier
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
81
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2009-06-18
繳交日期
Date of Submission
2009-07-06
關鍵字
Keywords
二維旁通乘法器、低功率、全數位頻率合成器
low power, all digital frequency synthesizer, 2-dimensional Bypassing Multiplier
統計
Statistics
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中文摘要
本論文包含兩個主題,第一個主題是使用Flying Adder架構之全數位頻率合成器;第二個主題是低功率低延遲二維旁通有號乘法器。
在第一個研究主題中,使用台灣積體電路 (Taiwan Semiconductor Manufacturing Company,TSMC) 0.18 μm 1P6M CMOS標準元件庫製程之設計方式,完成全數位頻率合成器。不但有效縮短設計時間,亦同時提高電路之可攜性與重覆使用性。本設計提供穩定的時脈訊號,可整合於系統單晶片中,也可快速的切換頻率,不需要過於冗長的切換時間,適用於不同時脈頻率的系統。
在第二個研究主題中,將Baugh-Wooley演算法結合二維旁通元件,完成低功率二維旁通有號乘法器,當乘法器中列(row)部份乘積或者行(column)乘積為零時,旁通元件將跳過多餘的計算單元以免會產生多餘的轉態訊號,因而節省功率消耗。本設計以全數位化及可參數化,以達到可在系統單晶片時代快速整合的目標。
Abstract
This thesis includes two topics. The first topic is an ADFS(All Digital Frequency Synthesizer)using a Flying Adder architecture. The second one is a low-power and low-latency 2-dimensional bypassing signed multiplier.
In the first topic, the ADFS is implemented by only using the standard cell library of TSMC(Taiwan Semiconductor Manufacturing Company)0.18 μm 1P6M CMOS process. The turn-around time is effectively reduced. Furthermore, the portability and reusability of the proposed design is significantly enhanced. The design provides stable clock signals with fast switching time.
In the second topic, the proposed multiplier is carried out by Baugh-Wooley algorithm using 2-dimensional bypassing units. The proposed bypassing units automatically skip redundant signal transitions when either the horizontally(row)partial products or vertically(column)operands are zero.
目次 Table of Contents
致謝 i
摘要 ii
Abstract iii
目錄 iv
圖目錄 vii
表目錄 x
第一章 概論 1
1.1 研究動機 1
1.1.1 頻率合成器 1
1.1.2 乘法器 3
1.2 相關技術與文獻探討 4
1.2.1  使用Flying Adder架構之全數位頻率合成器 4
1.2.2 低功率低延遲二維旁通有號乘法器 6
1.3 論文架構 7
第二章 使用Flying Adder架構之全數位頻率合成器 8
2.1 簡介 8
2.2 電路架構 9
2.3 電路設計 10
2.3.1 Flying Adder電路 12
2.3.2 延遲串(Delay chain)電路 16
2.3.3 ADPLL 17
2.4 電路模擬與晶片量測 26
2.4.1 電路模擬與分析 26
2.4.2 晶片實作 30
2.4.3 預計規格 32
2.5 晶片量測之討論 33
2.5.1 晶片量測結果討論 36
第三章 低功率低延遲週期之二維旁通有號乘法器 40
3.1 簡介 40
3.1.1 Baugh-Wooley演算法分析 41
3.2 電路設計 43
3.2.1  列旁通(Row bypassing)無號乘法器 43
3.2.2  行旁通(Column bypassing)無號乘法器 45
3.2.3 雙向式旁通設計 47
3.2.4 旁通邏輯的加法器單元 49
3.2.5 大型乘法器之骨牌效應 53
3.3 電路模擬與晶片實作 54
3.3.1 電路模擬與分析 54
3.3.2 晶片實作 56
3.3.3 預計規格 57
3.4 晶片量測之討論 60
3.4.1 晶片量測結果討論 62
第四章 結論與成果 64
參考文獻 66
參考文獻 References
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