本論文中，我們提出一個具有抬高本體與雙嵌入氧化物之單載子互補金氧半反相器(Unipolar CMOS)。單載子互補式金氧半其操作為藉由兩顆同為負型金氧半場效電晶體(NMOS)來取代傳統正型(PMOS)與負型(NMOS)金氧半所組成的反相器，且傳輸載子均為電子。同時，負載端藉由抬高本體與雙嵌入氧化物之NMOS來阻絕反轉層電流，使得以貫穿電流為主要操作電流，且達到與傳統PMOS之相同特性。
根據模擬結果顯示，本論文所提出之非傳統單載子架構在邏輯電路上均有正確的邏輯特性，且在隨機補償下，可加以驗證其趨勢。在製程部分，因驅動端(Q1)與負載端(Q2)同樣由NMOS所組成，故可除去N型井之製程步驟與共享輸出電極，且不須因載子移動率不同而做寬度之補償，因此在規劃佈局圖時，整體面積相較於傳統互補金氧半反相器減少73 %，使組合成邏輯電路時也能有效降低面積與成本。在貫穿效應機制的運用下，傳遞延遲時間也比傳統互補金氧半反相器下降了42 %。另外，我們將元件功函數改變，使元件在弱反轉區操作，可以有效減緩反轉層電流的產生與降低漏電流之效果，故在評量指標的表現上，相較於傳統互補金氧半有了46 %之改善。

In this thesis, we propose a unipolar CMOS with elevated body and Two-embedded oxide (EBTEO).The operation of the unipolar CMOS that the NMOS driver and the EBTEO NMOS load are presented to replace the conventional PMOS and NMOS. And the channel carriers are composed of electrons only. Meantime, the EBTEO structure can separate the inversion current, so the guiding current is the punch through current and it can achieve the PMOS characteristics in the EBTEO NMOS load. According to the simulation results, our proposed devices can achieve correct logical characteristics and further prove the trend in random compensation. Due to all NMOS devices are used in our structure, the N-well process can be removed, the output contact can be shared, and the load design does not have to compensate the layout width. So the layout areas can be reduced 73 %. The fabrication areas and cost can be reduced in logic circuits. The delay time of our proposed CMOS can reduce 42 % when compared with the conventional CMOS. In addition, the sub-threshold region unipolar CMOS can be formed by changing the gate work function. So, it can improve 46 % in the figure of merit (FOM) when compared with the conventional CMOS.

論文審定書……………………………………………………………………………....i
英文論文審定書………………………………………………………………………...ii
致謝……………………………………………………………………………………..iii
摘要...…………………………………………………………………………………...iv
Abstract ……………………………………………………………………………….....v
第一章 緒論 1
1.1 背景 1
1.2 動機 3
第二章 傳統與單載子互補金氧半之操作原理 5
2.1 貫穿效應 5
2.2 傳統互補金氧半反相器 7
2.2.1 架構與操作原理 7
2.2.2 負載線 8
2.2.3 電壓與電流轉移特性曲線 9
2.3 抬高本體與雙嵌入氧化物之非傳統單載子傳輸互補金氧半反相器 11
2.3.1 實際元件製程步驟 11
2.3.2 模擬元件架構尺寸說明 13
2.3.3 操作原理 14
2.3.4 負載線 16
2.3.5 電壓與電流轉移特性曲線 18
2.3.6 電流向量 19
第三章 電性討論與分析 21
3.1 模擬使用之物理模型 21
3.2 元件模擬電性結果之分析與討論 22
3.2.1 具有抬高本體與雙嵌入氧化物負型金氧半負載之非傳統單極性互補金氧半反相器 22
3.2.2 具有抬高本體與雙嵌入氧化物負型金氧半之不同參數特性 24
第四章 電路與次臨界分析 37
4.1 數位邏輯電路模擬之應用 37
4.1.1 反或閘(NOR Gate) 37
4.1.2 反及閘(NAND Gate) 40
4.1.3 Pseudo-NMOS之反或閘(Pseudo-NMOS-NOR Gate) 43
4.1.4 Pseudo-NMOS之反及閘(Pseudo-NMOS-NAND Gate) 46
4.1.5 環形震盪器(Ring Oscillator) 49
4.1.6 互斥或閘(XOR Gate) 50
4.1.7 全加器(Full adder) 53
4.1.8 解碼器(Decoder) 56
4.1.9 乘法器(Multiplier) 59
4.1.10 多工器(Multiplexers) 63
4.1.11 骨牌CMOS邏輯(Domino CMOS logic) 66
4.1.12 RS正反器(RS Flip-flop) 69
4.1.13 D型正反器(D Flip-flop) 72
4.1.14 JK正反器(JK Flip-flop) 75
4.1.15 T型正反器(T Flip-flop) 78
4.1.16 靜態隨機存取記憶體(SRAM) 81
4.2 傳遞延遲時間(Propagation delay time)與評量指標(FOM)之比較 84
4.3 抬高本體與雙嵌入氧化物單載子互補金氧半與傳統互補金氧半之佈局面積比較 88
4.4 次臨界型之操作與討論 89
4.4.1 次臨界型操作之原理分析 90
4.4.2 次臨界型操作之單載子互補金氧半 97
4.4.3 次臨界型操作之數位邏輯電路模擬 99
4.4.4 次臨界型操作之傳遞延遲時間(Propagation delay time)與評量指標(FOM)比較 106
4.4.5 次臨界型操作之VDD變化 113
4.5 實作量測結果 115
第五章 結論與未來展望 118
5.1 結論 118
5.2 未來展望 119
參考文獻 120
附錄 126
A. 源極與汲極空乏區寬度計算 126
B. 閘極控制之空乏區寬度 127
C. 功函數差 129
D. 平帶電壓 129
E. 臨限電壓 130
個人著作 131

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[45] 陳冠宇，一個具有本體抬高式與雙嵌入氧化物之高速度且低成本非傳統互補金氧半，國立中山大學電機工程研究所碩士論文，民國一百零二年，頁55。