在本篇論文中，我們提出了兩種適用於超薄本體(Ultra-Thin Body)的SOI架構：分別為具有N型通道與隔離氧化層之垂直式電晶體(Vertical Transistor with N-channel and Isolation Oxide, NCIOVT)和具有N型通道與溝槽之垂直式電晶體(Vertical Transistor with N-channel and Trench, NCTVT)，並將其應用在單電晶體動態隨機存取記憶體(One Transistor Dynamic Random Access Memory, 1T-DRAM)。
傳統1T-DRAM在微縮時會面臨電荷儲存區域不足與超耦合效應(Super-coupling Effect)，所以我們提出垂直式架構，在相同面積下能往高度延展，比起平面式元件多了延伸的儲存區域，而且隔離氧化層結構可以將元件操作區域和儲存區域做物理性分離，讓儲存電荷遠離PN界面進而降低復合速率。由模擬結果顯示，在單端汲極偏壓操作下的NCIOVT元件和NCTVT元件表現，因垂直式架構延長通道的關係，可程式規劃窗(Programming Window, PW)較小，但在寫入狀態後，隔離氧化層架構能讓NCIOVT元件和NCTVT元件的資料保存時間(Data Retention Time, RT)分別達到660.54 ms和683.48 ms的表現，為國際半導體技術發展藍圖規劃的10.32倍和10.68倍。同時，於高溫狀態下的PW表現，NCIOVT元件僅有35 %左右的退化幅度，而NCTVT元件反而因為無接面式通道而上升，在溫度變化方面具有抵抗力。不僅如此，NCIOVT元件和NCTVT元件於電路陣列干擾方面，不但可以選擇改變偏壓來改善元件的干擾情形，而且也擁有低功率消耗、高寫入速度和可微縮化的優點，成為了解決1T-DRAM微縮議題的極佳方案。

In this thesis, we propose vertical transistor with n-channel and isolation oxide(NCIOVT) 1T-DRAM and vertical transistor with n-channel and trench(NCTVT) 1T-DRAM with ultra-thin body structure for silicon-on-insulator. As the conventional 1T-DRAM scales down, it faces the shortcoming of an insufficient charge storage region and Super-coupling Effect. In this work, we use the vertical structure to enlarge the height and have more extended stored charge region than the planar structure in the same area. The isolation oxide not only can separate physically the device operation and charge storage region but also greatly decrease the junction of the P-type body region and N-channel region, and even suppresses the recombination rate. Due to the extended channel of the vertical structure, the programming performances of the NCIOVT device and the NCTVT device for single drain bias operation are not well enough. Nevertheless, a longer retention time is obtained by the advantage of the isolation oxide. The retention time of the NCIOVT device and the NCTVT device are 660.54 ms and 683.48 ms respectively, and the respective performance are 10.32 and 10.68 times bigger than the value of ITRS. At high temperature condition, the NCIOVT and the NCTVT show great thermal immunity for PW. The PW value of the NCIOVT device degrades only 35 %. Besides, the increase of drain current with temperature tends to increase the PW for junctionless channel. Moreover, the NCIOVT device and the NCTVT device also have the advantages of low power consumption, high operation speed, and scalability. Meanwhile, we can improve the disturb condition by altering operation voltage. We believe that the NCIOVT device and the NCTVT device become the more promising structures for next generation 1T-DRAM.

論文審定書 i
英文論文審定書 ii
摘要 iii
Abstract iv
第一章 導論 1
1.1 研究背景 1
1.2 論文回顧 4
1.3 動機 11
第二章 操作原理 13
2.1 物理機制探討 13
2.2 元件操作說明 14
2.2.1 撞擊游離機制 14
2.2.2 閘極引致汲極漏電流機制 14
2.2.3 整合式閘極引致汲極漏電流與撞擊游離之機制 15
第三章 元件製程設計 17
3.1 理想模擬元件 17
3.1.1 NCIOVT模擬製程 17
3.1.2 NCTVT模擬製程 18
3.2 實作元件 20
3.2.1 NCIOVT實際製程 20
3.2.2 NCTVT實際製程 22
第四章 研究方法與結果討論 24
4.1 物理機制模型 24
4.2 元件架構說明 26
4.2.1 NCIOVT元件之架構 27
4.2.2 NCTVT元件之架構 30
4.3 NCIOVT元件之基本電性 32
4.3.1 輸出特性曲線 32
4.3.2 輸入特性曲線 34
4.4 NCTVT元件之基本電性 35
4.4.1 輸出特性曲線 35
4.4.2 輸入特性曲線 37
4.5 NCIOVT之元件記憶體特性 38
4.5.1 NCIOVT之可程式規劃視窗 (Programming Window, PW) 38
4.5.2 NCIOVT之單/雙端汲極偏壓操作及其特性表現討論 41
4.5.3 NCIOVT之可程式規劃窗 (Programming Window, PW) 44
4.5.4 NCIOVT之資料保存時間 (Data Retention Time, RT) 47
4.5.5 NCIOVT之溫度改變對元件記憶體特性的影響 51
4.5.6 NCIOVT之寫入速度 54
4.5.7 NCIOVT之功率消耗 58
4.5.8 NCIOVT之元件於電路陣列干擾探討 61
4.6 NCTVT之元件記憶體特性 65
4.6.1 NCTVT之可程式規劃視窗 (Programming Window, PW) 65
4.6.2 NCTVT之單/雙端汲極偏壓操作及其特性表現討論 69
4.6.3 NCTVT之可程式規劃窗 (Programming Window, PW) 73
4.6.4 NCTVT之資料保存時間 (Data Retention Time, RT) 77
4.6.5 NCTVT之溫度改變對元件記憶體特性的影響 80
4.6.6 NCTVT之寫入速度 83
4.6.7 NCTVT之功率消耗 87
4.6.8 NCTVT之元件於電路陣列干擾探討 90
4.7 實作結果與量測 94
第五章 結論與未來展望 97
5.1 結論 97
5.2 未來展望 99
參考文獻 100
附錄 108

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