現今支援ILP處理器並不具備分析指令，與主動對程式指令進行編排提升並行度之功能，只能依照經編譯器編譯過的指令順序進行指令抓取，再根據指令之間的相依性，盡量將能夠派發的指令向下派發以提升並行度。高效能需求的程式中，無論是影像處理或是目前主流發展的機器學習，其程式皆使用了大量的迴圈結構，因迴圈結構的特殊性，使支援ILP處理器難以提升並行度，需要利用編譯器對程式進行特殊編譯以提升程式並行度，此做法缺乏彈性且無法作用於已經編譯完成的程式。
本論文提出基於多重迴圈指令序列之語意分析之動態迴圈展開器，並將之設計在Hyperscalar架構的指令分析器上，此動態迴圈展開器之架構分為以下三個部分：(1)迴圈偵測單元、(2)展開控制單元、(3)迴圈展開單元。其根據訂定的語意對指令序列進行分析，找出迴圈之指令區間並蒐集資料，通過分析已蒐集的資料、迴圈之間的關係以及當前迴圈展開的情形，將迴圈程式分段展開、消除迴圈結構的特殊性，並在重新編排指令順序後，派送至處理器中的各個核心。
為了驗證加入動態迴圈展開器後對處理器效能的提升，將機器學習中大量使用的的卷積運算、矩陣乘積運算以及當前常被使用的AES中的 mix column，利用通用的

In today's ILP processors can't analyze the semantic information of instructions and change instruction series automatically to promote ILP.ILP processors can only fetch instructions sequentially and analyze the dependency between instructions then dispatch the instructions which data are prepared. High performance requirements program such as image processing or machine learning, contains a lot of loop structure. Loop’s particularity caused processors hard to promote ILP. Processors need to use special compiler to compile code, the method is inflexible and cannot be used to promote the code which had already been compiled.
This paper proposed dynamic loop unrolling mechanism based on semantic analysis of nested loop consists of three units in the architecture: loop detect unit (LDU), unrolling control unit (UCU) and loop unrolling unit (LUU). It will parse the semantic of instructions to find the closed interval of the loop body instructions, and collect the instruction’s information in the loop body. Dynamic loop unrolling mechanism cuts the instruction series of nested loop into several segments and unrolls it by the information from LDU and the situation of unrolling, then dispatch the instruction into cores.
The verifications use ARM instructions generated by

目錄
論文審定書...........................................................................i
致謝......................................................................................ii
摘要.....................................................................................iii
ABSTRACT…………………………………………………………………….……..iv
目錄 ……………………………………………………………………………….......v
圖次..................................................................................viii
第1章 緒論......................................................................1
1.1 研究動機 ......................................................................1
1.2 研究目標 ......................................................................2
1.3 論文架構 ......................................................................3
第2章 相關研究..............................................................4
2.1 超純量處理器..............................................................4
2.1.1 超純量處理器架構介紹.......................................4
2.1.2 亂序執行例外處理...............................................8
2.2 超多純量(Hyperscalar)處理器...................................8
2.2.1 超多純量處理器架構介紹...................................8
2.2.2 指令分析器........................................................10
2.2.3 虛擬共享暫存器檔案.........................................11
2.3 在pipeline及Superscalar處理器中提升迴圈效率....13
2.3.1 Loop Buffers ....................................................13
2.3.2 Loop Cache......................................................14
2.3.3 Branch Prediction............................................14
2.3.4 編寫程式時進行loop unrolling........................14
2.4 在VLIW處理器中提升迴圈執行效率.......................15
2.5 在超多純量架構中提升迴圈執行效率....................15
第3章 在超多純量架構中設計
基於多重迴圈指令序列之語意分析之動態迴圈展開器...17
3.1 基於多重迴圈語意分析之迴圈展開系統架構...........17
3.1.1 系統設計概念.....................................................17
3.1.2 系統架構.............................................................19
3.2 迴圈偵測單元.............................................................24
3.2.1 單層迴圈偵測.....................................................24
3.2.2 多重迴圈判斷.....................................................26
3.2.3 迴圈資料儲存格式.............................................27
3.2.4 迴圈資料儲存格式範例.....................................28
3.2.5 迴圈偵測單元架構............................................29
3.3 展開控制單元...........................................................31
3.3.1 外層迴圈資料處理............................................32
3.3.2 外層迴圈計數器資料補償................................34
3.3.3 迴圈之間指令資料處理....................................37
3.3.4 迴圈展開資料儲存格式....................................38
3.3.5 展開控制單元架構...........................................38
3.4 迴圈展開單元..........................................................40
3.4.1 消除重疊運算相依性........................................41
3.4.2 暫存器重新命名................................................43
3.4.3 迴圈間指令以及外層迴圈計數器資料補償指令處理..44
3.4.4 迴圈補償機制....................................................46
3.4.5 迴圈展開單元架構............................................48
3.5 迴圈展開器概述.......................................................50
第4章 模擬與驗證.......................................................51
4.1 模擬程式流程...........................................................51
4.1.1 模擬程式流程介紹............................................51
4.1.2 測試指令...........................................................53
4.2 模擬結果與分析.......................................................56
4.2.1 模擬結果..........................................................56
4.2.2 模擬結果分析...................................................58
第5章 結論..................................................................62
參考文獻..........................................................................63

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