Responsive image
博碩士論文 etd-0707106-102246 詳細資訊
Title page for etd-0707106-102246
論文名稱
Title
動態二維旁通低功率數位乘法器設計與低功率無感測器直流無刷馬達之換相控制單晶片設計
A Low-power 2-dimensional Bypassing Digital Multiplier Design and A Low-power Sensorless Micro-controller for Brushless DC motors
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
59
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2006-06-15
繳交日期
Date of Submission
2006-07-07
關鍵字
Keywords
乘法器、旁通、低功率、直流無刷馬達、無感測器
brushless DC motor, sensorless, low-power, multiplier, bypassing
統計
Statistics
本論文已被瀏覽 5685 次,被下載 0
The thesis/dissertation has been browsed 5685 times, has been downloaded 0 times.
中文摘要
本論文包含兩個主題,第一個主題是動態二維旁通低功率數位乘法器設計;第二個主題是低功率無感測器直流無刷馬達之換相控制單晶片設計。
本論文首先提到的動態二維旁通低功率數位乘法器設計,是一種以二維的旁通方法所設計的低功率數位乘法器,當乘法器中水平的部份乘積或者垂直的運算元為零時,旁通元件將跳過多餘的計算單元以免會產生多餘的轉態信號,因而節省功率消耗,這是一種兼具垂直與水平方向偵測是否為零之二維動態旁通的設計。從佈局後模擬的結果看來,使用動態旁通的8 × 8乘法器,比起傳統的矩陣型8 × 8乘法器約可以節省至少75%的功率消耗,但也相對的付出了少許的面積與延遲時間。
其次,本論文提到的低功率無感測器直流無刷馬達之換相控制單晶片設計,目的是為了達到直流無刷馬達無需透過傳統霍爾元件的回授訊號,仍可順利的進行直流無刷馬達的速度控制,此設計是採用直流無刷馬達端電壓量測方式的無感換相控制技術,藉由偵測未激發相反電動勢之零交越點,來估算出直流無刷馬達的換相時刻。
Abstract
This thesis includes two research topics. The first topic is a low-power 2-dimensional bypassing digital multiplier design. The second one is a low-power sensorless micro-controller for brushless DC motors (BLDCM).
The low-power 2-dimensional bypassing digital multiplier takes advantage of a 2-dimensional bypassing method. The proposed bypassing cells constituting the multiplier skip redundant signal transitions when the horizontally partial product or the vertically operand is zero. Hence, it is a 2-dimensional bypassing architecture. Thorough post-layout simulations show that the power dissipation of the proposed 8 × 8 design is reduced by more than 75% compared to the prior 8 × 8 design with obscure cost of delay and area.
The goal of the low-power sensorless micro-controller for brushless DC motors is to design a BLDCM controller without using any Hall sensor. Back-EMF estimation method using the terminal voltage sensing is adopted for the detection of the commutation moment for the proper commutation control of the BLDCM. The position of the rotor can be precisely estimated by measuring the back-EMF as well as the zero-crossing points.
目次 Table of Contents
摘要  i
Abstract  ii
第一章 簡介  1
1.1 前言  1
1.2 先前文獻探討  3
1.2.1 低功率數位乘法器  3
1.2.2 無感測器馬達換相控制  4
1.3 論文大綱  5
第二章 動態二維旁通低功率數位乘法器設計  6
2.1 概論  6
2.2 基本原理概述  7
2.3 雙向式旁通架構與原理說明  8
2.3.1 雙向式旁通設計  8
2.3.2 包含旁通邏輯的加法器單元  9
2.3.3 大型乘法器的骨牌效應  11
2.4 模擬與量測結果  14
2.4.1 模擬結果  14
2.4.2 晶片量測結果與分析討論  14
第三章 低功率無感測器直流無刷馬達之換相控制單晶片設計 19
3.1 概論  19
3.2 無感測器之轉子感應原理概述  20
3.3 整體架構與設計方式說明  24
3.3.1 整體電路架構  24
3.3.2 可變脈波寬度調變電路之設計與說明  24
3.3.3 換相偵測電路之設計與說明  27
3.3.4 類比數位轉換器之設計與說明  28
3.3.5 具有省電控制處理單元之8位元微控制器設計與說明  32
3.4 電路模擬結果  35
3.4.1 連續逼近類比數位轉換器之模擬結果  35
3.4.2 晶片外部電路測試結果  37
3.5 晶片製作  42

第四章 結論與成果  44
參考文獻  45
參考文獻 References
[1] C.-C.Wang, C.-J. Huang, and K.-C. Tsai, “A 1.0 GHz
0.6-µm 8-bit carry lookahead adder using PLA-styled
all-N-transistor logic,” IEEE Trans. of Circuits and
Systems, Part II : Analog and Digital Signal Process-
ing, vol. 47, no. 2, pp. 133-135, Feb. 2000.
[2] W. Hwang, G. D. Gristede, P. N. Sanda, S. Y. Wang,
and D. F. Heidel, “Implementation of a self-resetting
CMOS 64-bit parallel adder with enhanced testabil-
ity,” IEEE J. Solid-State Circuits, vol. 34, no. 8, pp.
1108-1117, Aug. 1999.
[3] T. Ahn, and K. Choi, “Dynamic operand interchange
for low power,” Electronics Letters, vol. 33, no. 25,
pp. 2118-2120, Dec. 1997.
[4] J. Choi, J. Jeon, and K. Choi, “Power minimization of
functional units by partially guarded computation,”
2000 International Symposium on Low Power Elec-
tronics and Design (ISLPED’00), pp. 131-136, July
2000.
[5] J. Di, J. S. Yuan, and M. Hagedorn, “Energy-aware
multiplier design in multi-rail encoding logic,” The 2002 45th Midwest Symposium on Circuits and Sys-
tems (MWSCAS-2002), vol. 2, pp. 294-297, Aug.
2002.
[6] S. Hong, S. Kim, M. C. Papaefthymiou, and W. E.
Stark, “Low power parallel multiplier design for DSP
applications through coefficient optimization,” 1999
Twelfth Annual IEEE International ASIC/SOC Con-
ference, pp. 286-290, Sep. 1999.
[7] J. Ohban, V. G. Moshnyaga, and K. Inoue, “Mul-
tiplier energy reduction through bypassing of partial
products,” 2002 Asia-Pacific Conference on Circuits
and Systems (APCCAS ’02), vol. 2, pp. 13-17, Oct.
2002.
[8] M.-C. Wen, S.-J. Wang, Y.-N. Lin, “Low power par-
allel multiplier with column bypassing,” 2005 Inter-
national Symposium on Circuits and Systems (IS-
CAS’05), vol. 2, pp. 1638-1641, May. 2005.
[9] M. Schroedl, and R. S.Wieser, “EMF-based rotor flux
detection in induction motors using virtual short cir-
cuits,” IEEE Trans. on Industry Applications, vol. 34,
pp. 142-147, Jan./Feb. 1998.
[10] K.-Y. Cheng, Y.-T. Lin, C.-H. Tso, Y.-Y. Tzou, “De-
sign of a Sensorless Commutation IC for BLDC Mo-
tors,” 2002 IEEE 33rd Annual Power Electronics Spe-
cialists Conference pp. 295-300, June 23-27, 2002.
[11] G. H. Jang. J. H. Park and J. H. Chang, “Posi-
tion detection and start-up algorithm of a rotor in
a sensorless BLDC motor utilizing inductance varia-
tion,” IEEE Proceedings-Electric Power Applications
vol. 149, no. 2, pp. 137-142, Mar. 2002.
[12] T.-H. Kim, B.-K. Lee, and M. Ehsani, “Sensorless
control of BLDC motor from near zero to high speed,”
Eighteenth Annual IEEE Applied Power Electronics
Conference and Exposition pp. 306-312, Feb. 9-13,
2003.
[13] Rohm Co. Ltd., “Coil load driving circuit.” Taiwan
Patent, NO. 336310, July. 1998.
[14] P. R. Gray, R. G. Meyer, “Analysis and design of
analog integrated circuits,” John Wiley & Sons, Feb.
2001.
[15] C.-C. Wang, G.-N. Sung, “A Low-Power 2-
Dimensional Bypassing Multiplier Using 0.35 um
CMOS Technology,” 2006 IEEE Computer Society
Annual Symposium on VLSI (ISVLSI 2006), vol 00,
pp. 405-410 02-03 Mar. 2006.
[16] C.-C. Wang, K.-W. Fang, “Dual-OPA coil driver for
heat dissipation of SOCs,” 2005 The 16th VLSI De-
sign/CAD Symposium, (VLSI-CAD 2005), P1-1, CD-
ROM version, Aug. 2005.
[17] A. Wu, “High performance adder cell for low power
pipelined multiplier,” 1996 International Symposium on Circuits and Systems (ISCAS’96),vol. 4, pp. 57-60,
May 1996.
[18] C. P. Lerouge, P. Girard, and J. Colardelle, “A fast
16-bit NMOS parallel multiplier,” IEEE J. Solid-State
Circuits, vol. SC-19, pp. 338-342, Mar. 1984.
[19] Allegro, “3-Phase Brushless DC Motor Con-
troller/Driver with Back-EMF Sensing,” 8902A
Datasheet, Nov. 1995.
[20] R. Mizutani, T. Takeshita, and N. Matsui, “Current
model-based sensorless drives of salient-pole PMSMat
low speed and standstill,” IEEE Trans. Ind. Applicat.,
vol. 34, no. 4, pp. 841-846, July/August 1998.
[21] N. Matsui and T. Takeshita, “A novel starting method
of sensorless salient-pole brushless DC motor,” IEEE
IAS Annual Meeting Conf. Rec., vol. 1, pp. 386-392,
Oct. 1994.
[22] R. Dhaouadi, N. Mohan, and I. Norum, “Design and
implementation of an extended Kalman filter for the
state estimation of a permanent magnet synchronous
motor,” IEEE Trans. Power Electron, vol. 6, pp. 491-
497, July. 1991.
電子全文 Fulltext
本電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。
論文使用權限 Thesis access permission:校內校外均不公開 not available
開放時間 Available:
校內 Campus:永不公開 not available
校外 Off-campus:永不公開 not available

您的 IP(校外) 位址是 18.191.228.88
論文開放下載的時間是 校外不公開

Your IP address is 18.191.228.88
This thesis will be available to you on Indicate off-campus access is not available.

紙本論文 Printed copies
紙本論文的公開資訊在102學年度以後相對較為完整。如果需要查詢101學年度以前的紙本論文公開資訊,請聯繫圖資處紙本論文服務櫃台。如有不便之處敬請見諒。
開放時間 available 已公開 available

QR Code