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博碩士論文 etd-0707106-140908 詳細資訊
Title page for etd-0707106-140908
論文名稱
Title
全植入式神經訊號監測系統與低功率循序存取記憶體
A Fully Implantable Neural Signal Monitoring System and A Low-power Sequential Access Memory
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
71
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2006-06-15
繳交日期
Date of Submission
2006-07-07
關鍵字
Keywords
循序存取、記憶體、植入式、神經訊號、低功率
Memory, Implantable, Neural Signal, Low-power, Sequential Access
統計
Statistics
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中文摘要
當人體的神經元細胞受損,導致中央神經系統發生動作失序的情形時,我們可以使用微電刺激的方式,代替中央神經系統來傳遞控制訊號給肢體或器官。本論文的第一個部份提出一個可以完全植入至生物體內的神經微電刺激及神經訊號監測系統,並對系統的通訊協定以及基頻電路部份做詳細的介紹。

隨著小型化及攜帶式電子裝備的快速發展,由於電池容量的限制,低功率的重要性逐漸提升,而嵌入式記憶體也在此類系統中消耗了可觀的功率。因此本論文的第二部份,提出了一個低功率的記憶體循序解碼器,並藉由實做一個2Kb的靜態記憶體,以驗證我們提出的循序解碼器,能夠降低記憶體的功率消耗。
Abstract
When the nerve cell of human is damaged, the central neural system (CNS) can not work properly. Instead of sending commands by CNS, we can use a micro-stimulation method to send commands to hands, legs, or organs. The first part of this thesis presents a fully implantable system for neural micro-stimulation and neural signal monitoring, and introduces the communication protocol and baseband circuitry of the system.

Due to the rapidly development of small and portable electrical equipments, low power becomes more and more important because of the limitation of the battery capacity. Meanwhile, the embedded memory in these devices consumes considerable power. In this thesis, we present a low-power sequential memory decoder to resolve the power-dissipation of embedded memories. We’ll verify that the sequential decoder can reduce the power consumption compared to traditional decoders by implementing our idea with a 2-Kbit SRAM memory.
目次 Table of Contents
摘要 i


Abstract ii

第一章 前言 1
1.1 論文動機 1
1.2 植入式生醫晶片相關技術介紹 3
1.3 低功率記憶體相關技術介紹 5
1.4 論文架構 6

第二章 全植入式神經微電刺激及神經訊號監測系統 7
2.1 系統架構及簡介 7
2.2 系統通訊協定與基頻電路 11
2.2.1 系統通訊協定 11
2.2.2 基頻電路 22
2.3 晶片佈局與系統規格 26
2.3.1 晶片佈局 26
2.3.2 系統規格列表 27
2.4 晶片測試結果 28
2.5 討論 29

第三章 低功率循序存取記憶體 31
3.1 系統架構 31
3.2 電路介紹 32
3.2.1 循序解碼器 32
3.2.2 SRAM的讀寫 39
3.2.3 SRAM詳細電路圖 41

3.3 佈局與模擬 42
3.3.1 循序解碼器模擬結果 43
3.3.2 隨機存取解碼器模擬結果 46
3.4 晶片量測 48
3.4.1 循序解碼器量測結果 49
3.4.2 隨機存取解碼器量測結果 51
3.4.3 整體量測結果 53
3.5 討論 53

第四章 結論與展望 54

參考文獻 56
參考文獻 References
[1] A. M. Leung, W. H. Ko, T. M. Spear, and J. A. Bettice, “Intracranial pressure telemetry system using semicustom integrated circuits,” IEEE Trans. Biomed. Eng., vol. BME-33, no. 4, pp. 386–395, Apr. 1986.
[2] M. G. Dorman, M. A. Prisbe, and J. D. Meindl, “A monolithic signal processor for a neurophysiological telemetry system,” IEEE. J. Solid-State Circuits, vol. SC-20, no. 6, pp. 1185–1193, Dec. 1985.
[3] B. Smith, P. H. Peckham, M. W. Keith, and D. D. Roscoe, “An externally powered, multichannel, implantable stimulator for versatile control of paralyzed muscle,” IEEE Trans. Biomed. Eng., vol. BME-34, no. 7, pp. 499–508, July 1987.
[4] H. V. Allen, J. W. Knutti, and J. D. Meindl, “Integrated power controllers and RF data transmitters for totally implantable telemetry,” Biotelemetry Patient Monit., vol. 6, no. 3, pp. 147–159, 1979.
[5] D. C. Galbraith, “An implantable multichannel neural stimulator,” Ph.D. dissertation, Stanford Univ., Stanford, CA, Dec. 1984.
[6] K. W. Horch and G. S. Dhillon, Neuroprosthetics: Theory and Practice, Series on Bioengineering & Biomedical Engineering, vol. 2. World Scientific Publishing, 2004.
[7] E. M. Schmidt, et al. “Feasibility of a visual prosthesis for the blind based on intracortical microstimulation of the visual cortex,’’ Brain, vol. 119, no.2, pp. 507–522, 1996.
[8] O. Minato, T. Masuhara, T. Sasaki, K. Matsumoto, Y. Sakai, and T. Hayashida, “A 20 ns 64K CMOS static RAM,” IEEE Journal of Solid-State Circuits, vol. 19, no. 6, pp. 1008-1013, Dec. 1984.
[9] C. M. Zierhofer, I.J. Hochmair-Desoyer, and E.S. Hochmair, “Electronic design of a cochlear implant for multichannel high-rate pulsatile stimulation strategies,” IEEE Trans. Rehab. Eng., vol. 3, no. 1, pp. 112–116, March 1995.
[10] B. Aouizerate, E. Cuny, C. Martin-Guehl, D. Guehl, H. Amieva, A. Benazzouz, C. Fabrigoule, M. Allard, A. Rougier, B. Bioulac, J. Tignol, and P. Burbaud, “Deep brain stimulation of the ventral caudate nucleus in the treatment of obsessive-compulsive disorder and major depression. Case report,’’ J Neurosurg., vol. 101, no. 4, pp. 682–686, Oct. 2004.
[11] Bragin, J. Hetke, C. L. Wilson, D. J. Anderson, J. Engel, and G. Buzsaki, “Multiple site silicon-based probes for chronic recordings in freely moving rats: implantation, recording and histological verification,’’ Journal of Neuroscience Methods, vol. 98, no.1, pp. 77–82, 2000.
[12] S. Boyer and M. Sawan, et al., “Implantable selective stimulator to improve bladder voiding: Design and chronic experiments in dogs,” IEEE Trans. Rehab. Eng., vol. 8, no. 4, pp. 464–470, Dec. 2000.
[13] S. Hattori, and T. Sakurai, “90% write power saving SRAM using sense-amplifier memory cell,” in Proc. Symp. on VLSI Circuits, pp. 46-47, June 2002.
[14] M. D. Gingerich, J. F. Hetke, D. J. Anderson, and K. D. Wise, “A 256-Site 3D CMOS Microelectrode Array for Multipoint Stimulation and Recording in the Central Nervous System,” presented at Int. Conf. on Solid-State Sensors and Actuators, Munich, June 2001.
[15] K. D. Wise, “Wireless implantable microsystems coming breakthroughs in health care,’’ Circuits Digest of Technical Papers, Symposium on VLSI, pp. 106–109, 2002.
[16] G. Gudnason and E. Bruun, “CMOS Circuit Design for RF Sensors,’’ Kluwer, 2002.
[17] W. Shiue, and C. Chakrabarti, “Memory Design and Exploration for low power, embedded systems,” 36th ACM/IEEE Design Automation Conf., pp. 140-145, Jun. 1999.
[18] M. Mehendaule, S. Sherlekar, and G. Venkatesh, “Low-power realization of FIR filters on programmable DSP’s,” IEEE Trans. Very Large Scale Integration Systems, vol. 6, no. 4, pp. 546-553, Dec. 1998.
[19] P. K. Lala, and A. Walker, “An on-chip test scheme for SRAMs,” Inter. Workshop on Memory Technology, Design and Testing, pp. 16-20, Aug. 1994.
[20] C.-C Wang, J.-M Huang, and H.-C Cheng, “A 2K/8K mode smallarea FFT processor for OFDM demodulation of DVB-T receivers,” IEEE Trans. on Consumer Electronics, vol. 5, no. 1, pp. 28-32, Feb. 2005.
[21] B. Razavi, Principles of Data Conversion System Design. NJ: IEEE press, 1995.
[22] C.-C. Wang, T.-J. Lee, Y.-T. Hsiao, U. F. Chio, C.-C. Huang, C.-J. Chen , and Y.-H. Hsueh, “A multi-parameter implantable micro-stimulator SOC,” IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 13, no. 12, pp. 1399-1402, Dec. 2005.
[23] C.-C. Wang, Y.-H. Hsueh, Y.-T. Hsiao, and U. F. Chio, “Design of a Wireless Transceiver for Implantable Neural Interface,” 2003 Inter. Symp. on Communications, pp. 69 (CD-ROM version), Dec. 2003.
[24] C.-C. Wang, Y.-H. Hsueh, Y.-T. Hsiao, U Fat Chio, C.-C. Huang, and P.-L. Liu, “An Implantable Neural Interface Micro-stimulator Chip with External Controllability,” 2004 The Fourth IEEE Asia-Pacific Conference on Advanced System Integrated Circuits (AP-ASIC'2004), pp. 356-359, Aug. 2004.
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