在本論文的第一部份我們提出了一個八位元，20-MS/s取樣頻率的管線式類比數位轉換器。我們使用了一種sharing amplifiers的技術以減少放大器的數量，並且使用動態比較器來降低功率消耗。我們所提出的設計在0.35μm CMOS製程下實現。模擬結果顯示在3.3伏特的供應電壓下，最大的功率消耗為45 mW，且輸入為5 MHz的正弦波得到45 dB的SFDR。
論文第二部分中我們描述了一個應用於868/915 MHz頻帶之ZigBee接收機中五位元，2.4 MHz取樣頻率的低功率類比數位轉換器。此轉換器採用的是連續逼近式的架構。使用0.18 μm CMOS製程下，模擬結果顯示最差的功率消耗僅449.6 μW。此轉換器達成最大的差異非線性度為0.3 LSB，最大的累積非線性度為0.5 LSB。

The first topic of this thesis proposes an 8-bit, 20 MSample/s pipeline analog-to-digital converter (ADC). The sharing amplifiers technique is employed to reduce the overall number of the amplifiers wherein dynamic comparators are adopted to reduce the power consumption. The proposed design is implemented by 0.35 μm CMOS technology. The simulation results show that maximum power consumption is 45 mW given a 3.3 V power supply, and the SFDR is 45 dB with a sinusoidal input at 5 MHz.
The second topic is to describe a 5-bit, 2.4 MSample/s, low power analog-to-digital converter for ZigBee receiver using 868/915 MHz band. The converter uses the successive approximation architecture. By using 0.18 μm CMOS technology, the simulation results show the worst-case power consumption is merely 449.6 μW. The converter achieves the maximum differential nonlinearity of 0.3 LSB, the maximum integral nonlinearity of 0.5 LSB.

目錄
摘要 i
Abstract ii
第一章 簡介 1
1.1 前言 1
1.2 文獻探討 3
1.2.1 八位元20-MS/s管線式類比數位轉換器 3
1.2.2 應用於ZigBee接收機之低功率五位元2.4-MS/s
連續逼近式類比數位轉換器 3
1.3 論文大綱 5
第二章 八位元20-MS/s管線式類比數位轉換器 6
2.1 簡介 6
2.2 電路架構與原理說明 7
2.2.1 S/H電路 8
2.2.2 1.5-bit ADC stage電路 8
2.2.3 sharing amplifiers電路 11
2.2.4 dynamic comparator電路 14
2.2.5 錯誤更正電路 15
2.2.6 不重疊時脈電路 16
2.2.7 穩壓電路 16
2.2.8 操作放大器規格考量 18
2.2.9 timing分析 19
2.3 模擬結果 20
2.3.1 輸出波形 20
2.3.2 DNL/INL 21
2.3.3 SFDR 22
2.3.4 規格列表 23
2.3.5 效能比較 23
2.3.6 佈局考量 24
2.3.7 佈局圖 25
2.4 晶片量測 26
2.4.1 穩壓電路 26
2.4.2 ADC輸出波形 29
2.4.3 結論與討論 29
第三章 應用於ZigBee接收機之低功率五位元2.4-MS/s
連續逼近式類比數位轉換器 32
3.1 簡介 32
3.2 電路架構與原理說明 34
3.2.1 CONTROL與SAL電路 35
3.2.2 Sample-and-subtract電路 36
3.2.3 動態比較器電路 37
3.3 模擬結果　 38
3.3.1 DNL與INL分析結果 39
3.3.2 SFDR模擬結果 40
3.3.3 規格列表 41
3.3.4 效能比較 41
3.3.5 佈局考量 42
3.3.6 佈局圖 42
第四章 結論與成果 44

參考文獻 47

參考文獻

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