本論文的第一部份提出一個使用電荷回收機制之低電壓傳送器，內含一個低電壓差動傳送器電路與電荷回收再利用電路。使用低電壓差動訊號對來達到低功率與得到高抗雜訊能力，並利用電荷回收策略來回收電荷再利用，更進一步降低功率消耗。
第二部份則為適用於數位電視地面廣播系統( digital video broadcasting over terrestrial, DVB-T )接收器中編碼正交分頻多工解調器( Coded orthogonal frequency division multiplex demodulation, COFDM demodulation )，能對抗訊號頻率飄移，並能動態調整快速傅立葉轉換處理器輸入訊號框架來同步訊號起點，並執行2K/8K兩種解調模式。此解調器的方塊主要可分為四個主要部份：時間同步修正、頻率同步修正、雙模2K/8K快速傅立葉轉換處理器與通道估測修正。

The first topic of this thesis presents a bus driver design which is based on a charge recycle technique. The proposed design is mainly composed of a differential low swing circuit and a charge recycling circuit. The differential low swing signaling has been adopted to achieve low power and robust data transmission. The charge recycle is utilized to reduce power dissipation on long lines for the differential low swing signaling.
The second topic is the coded orthogonal frequency division multiplex demodulation (COFDM) demodulator compliant with the European digital video broadcasting over terrestrial (DVB-T). It can recover the frequency offset of COFDM signal and dynamically select the FFT stages to synchronize the start of a symbol. The proposed design mainly contains four blocks : a time synchronization block, a frequency synchronization block, a 2K/8K FFT processor, and a channel estimation block.

摘 要 i
Abstract ii
第一章 前言與簡介 1
1.1 前言 1
1.2 文獻探討 2
1.2.1 使用電荷回收機制之低電壓傳送器 2
1.2.2 適用於DVB-T之編碼正交分頻多工解調器 3
1.3 論文大綱 5
第二章 使用電荷回收機制之低電壓傳送器 6
2.1 簡介 6
2.2 電路架構與原理說明 6
2.2.1 低電壓傳送器 6
2.2.2 電荷回收機制 9
2.2.3 功率消耗分析 11
2.3 模擬結果 12
2.4 量測結果與討論 19
第三章 適用於DVB-T之編碼正交分頻多工解調器 25
3.1 簡介 25
3.2 原理與架構說明 25
3.2.1 時間同步修正 27
3.2.2 頻率同步修正 29
3.2.3 雙模2K/8K快速傅立葉轉換處理器 33
3.2.4 通道估測修正 36
3.2.5 整體系統架構實現 38
3.3 模擬結果 39
3.4 量測結果與討論 46
第四章 結論與成果 50
參考文獻 52

[1]
A. Rjoub, and O. Koufopavlou, “Low-swing/low power driver architecture,” The 1999 IEEE International Conference on Electronics, Circuits and Systems (ICECS 1999), vol. 2, pp. 636-642, Sept. 1999.
[2]
C.-K Kwon, K.-M. Rho, and K. Lee, “High speed and low swing interface circuits using dynamic over-driving and adaptive sensing scheme,” The International Conference on VLSI and CAD (ICVC 1999), pp. 388-391, Oct. 1999.
[3]
V. Kursun, R. M. Secareanu, and E. G. Friedman, “CMOS voltage interface circuit for low power systems,” The2002 IEEE International Symposium on Circuits and Systems (ISCAS 2002), vol. 3, pp. 667-670, May 2002.
[4]
R. Ho, K. Mai, and M. Horowitz, “Efficient on-chip global interconnects,” The 2003 Symposium on VLSI Circuits, pp. 271-274, June 2003.
[5]
A. Narasimhan, M. Kasotiya, and R. Sridhar, “A low- swing differential signaling scheme for on-chip global interconnects,” The 18th International Conference on VLSI Design, pp. 634-639, Jan. 2005.
[6]
C.-C. Wang, Y.-L. Tseng, C.-S. Chen, and R. Hu, “38.9 uW/MHz small-area digital I/O cell,” 2003 The 14th VLSI Design/CAD Symposium, pp. 66, C4-7, Aug. 2003.
[7]
M. Hahm, “Modest power savings for applications dominated by switching of large capacitive loads,” IEEE Symposium on Low Power Electronics, pp. 60-61, Oct. 1994.
[8]
E. D. Kyriakis- Bitzaros, and S. S. Nikloaidis, “Design of low power CMOS drivers based on charge recycling,” The 1997 IEEE International Symposium on Circuits and Systems (ISCAS 1997), vol. 3, pp. 1924-1927, June 1997.
[9]
I. Bouras, Y. Liaperdos, and A. Arapoyanni, “A high speed low power CMOS clock driver using charge recycling technique,” The 2000 IEEE International Symposium on Circuits and Systems (ISCAS 2000), vol. 5, pp. 657-660, May 2000.
[10]
M. K. Karlsson, M. Vesterbacka, and L. Wanhammar, “Low-swing charge recycle bus drivers,” The 1997 IEEE International Symposium on Circuits and Systems (ISCAS 1998), vol. 2, pp. 127-130, June 1998.
[11]
H. Zang, V. George, and J. M. Rabaey, “Low-swing on-chip signaling techniques: effectiveness and robustness,” IEEE Trans. on Very Large Scale Integration, vol. 8, no. 3, pp. 264-273, June 2000.
[12]
European Telecommunications Standards Institute (ETSI) ETSI 300 744 v1.1.2(1997-08): Digital Video Broadcasting (DVB); Framing Structure, Channel Coding and Modulation for Digital Terrestrial Television.
[13]
C. Del Toso, P. Combelles, J. Galbrun, L. Lauer, P. Penard, P. Robertson, F. Scalise, P. Senn, L. Soyer, “0.5-μm CMOS circuits for demodulation and decoding of an OFDM-based digital TV signal conforming to the European DVB-T standard,” IEEE J. of Solid-State Circuits, vol. 33, no. 11, pp. 1781-1792, Nov. 1998.
[14]
K.-Y. Jheng, T.-H. Wu, Y.-C. Wang, J.-C. Yeo, Y.-J. Cho, A.-Y. Wu, “A DVB-T baseband demodulator design based on multimode silicon IPs,” 2005 IEEE VLSI-TSA International Symposium, pp. 49 -52, Apr 2005.
[15]
R. Makowitz, A. Turner, J. Gledhill, and M. Mayr, “A single-chip DVB-T receiver,” IEEE Trans. on Consumer Electronics, vol. 44, no. 3, pp. 990-993, Aug. 1998.

[16]
S. Anikhindi, G. Cradock, R. Makowitz, C. Patzelt, “A commercial DVB-T demodulator chipset,” 1997. International Broadcasting Convention, pp. 528-533, Sept. 1997.
[17]
M. Tognin, L. Soyer, P. Combelles, C. Del Toso, D. Hepper, G. Piccinini, J. J. Ma, F. Nicolas, P. Robertson, F. Scalise, and A. Dener, “A VLSI solution for a digital terrestrial TV (DVB-T) receiver,” 1997 International Broadcasting Convention, pp. 343-348, Sept. 1997.
[18]
M. Massel, Digital television DVB-T, COFDM, and ATSC 8-VSB, Digitaltvbooks.Com, 2000.
[19]
J. H. Stott, “The DVB terrestrial (DVB-T) specification and its implementation in a practical modem,’’ International Broadcasting Convention, pp. 255-260, Sept. 1996.
[20]
D. Lee, and K. Cheun, “A new symbol timing recovery algorithm for OFDM systems,” IEEE Trans. on Consumer Electronics, vol. 43, no. 3, pp. 767-775, Aug. 1997.
[21]
H. Nogami, and T. Nagashima, “A frequency and timing period acquisition technique for OFDM systems,” 1995 IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC’95), vol. 3, pp. 1010-1015, Sept. 1995.
[22]
J. Echavarri, M. E. Woodward, and S. K. Barton, “A comparison of time and frequency synchronisation algorithms for the European DVB-T system,” 1999 IEEE Vehicular Technology Conference (VTC 1999), vol. 2, pp. 678-682, Sept. 1999.
[23]
C.-C. Wang, J.-M. Huang and H.-C. Cheng, “A 2K/8K Mode Small-Area FFT Processor for OFDM Demodulation of DVB-T Receivers,” IEEE Trans. on Consumer Electronics, vol. 51, no. 1, pp. 28-32, Feb. 2005.
[24]
J.-H. Suk, D.-W. Kim, T.-W. Kwon, S.-K. Hyung, and J.-R. Choi, “A 8192 complex point FFT/IFFT for COFDM modulation scheme in DVB-T system,” 2003 International SOC (System-on-Chip) Conference, vol. 5, pp. 131-134, Dec. 2003.
[25]
C.-C. Wang, J.-M. Huang, and Y.-M. Tseng, “Low-Power Bus Driver Design Based on A Charge Recycle Technique,” 2005 The 16th VLSI Design/CAD Symposium, P1-8, CD-ROM version, Aug. 2005
[26]
C.-C. Wang, J.-M. Huang, and Y.-M. Tseng, “A 0.18um CMOS Prototype of COFDM Demodulator for European DVB-T Standard,” 2006 IEEE VLSI-DAT International Symposium, pp. 56-60, Apr. 2006.