本論文包含兩個主題：以非均分拋物線內插法實現之無唯讀記憶體直接頻率合成器(DDFS)與頻移讀取電路，均實現於一個快篩IgE感測生醫晶片系統。
第一個主題提出一生醫IgE蛋白質濃度訊號讀取系統，並利用TSMC 1P6M 0.18 μm製程實現一生醫頻移讀取電路。本論文結合彎曲平板波(flexural plate-wave, FPW)生醫感測晶片，並將包含控制區塊、數位類比轉換器、壓控震盪器、訊號放大器、峰值偵測器、暫存器及減法器等電路實現於單一晶片。本論文係利用彎曲平板波晶片因負載蛋白質濃度不同而中心頻率偏移的現象，藉由產生一掃頻訊號，同時通過兩個彎曲平板波生醫感測晶片，其中一為實驗組，另一為對照組。讀取各自中心頻率，計算位移量後，可由查表法得到蛋白質負載濃度。相較於傳統醫療檢測儀器，本論文之生醫頻移讀取電路不僅可在10分鐘內得知檢測結果，更可大幅降低檢測的費用，更適於現今重點照護的醫療需求。
第二個主題探討π/ 2弧度弦波之分割方式以改善無雜訊動態範圍，並且利用TSMC 2P4M 0.35 μm製程來實現一無唯讀記憶體直接頻率合成器，係使用在本論文前一主題之讀取系統中。本論文提出之非均分拋物線內插法，係基於弦波的對稱性，僅需以π/ 2弧度弦波即可得到一完整弦波。本非均分拋物線內插法為將π/ 8弧度弦波區段使用同一拋物線係數，並將π/ 8至π/ 2弧度弦波區段平均分為十五段，並採用十五組拋物線係數來取得弦波數位值。在同樣十六區段的分段條件，本論文結合類線性內插法與位移式拋物線內插法以取得π/ 2弧度弦波數位值。此分段方法不僅可減小實際弦波與理想弦波的誤差，更可改善無雜訊動態範圍。

This thesis consists of two topics. A frequency-shift readout circuit is integrated for the rapid IgE measurement biomedical system in the first half. Secondly, we present a ROM-less DDFS (direct digital frequency synthesis) using a non-equal division parabolic polynomial interpolation method, which is used as the frequency generator in the measurement system.
The first topic investigates the IgE concentration measurement system and realizes the readout circuit using TSMC 1P6M 0.18 μm CMOS technology. We integrate the flexural plate wave (FPW) sensor chips and an ASIC comprising control block, digital to analog convertor (DAC), OTA-C oscillators, amplifiers, peak detectors, registers, and a subtractor. By taking advantages of the characteristics that the central frequencies of the loaded FPW sensors will be shifted, sine waves with various frequencies are generated and swept through one pair of FPW sensors. The frequency difference of these sensors is then readout to get concentration by look-up table.
The second topic investigates the division method of a quarter sine wave to improve the spurious free dynamic range (SFDR) and realizes a ROM-less DDFS which is used as the frequency generator in the mentioned IgE measurement system. The proposed non-equal division parabolic polynomial interpolation method will generate a complete sine wave by a quarter of a sine digital signal owing to the symmetry. We combine the quasi-linear interpolation and an offset adjustment to derive the quarter sine wave digital signals. The proposed method not only reduces the absolute error between ideal sine wave and generated sine wave, it also improves SFDR.

致謝 ................................................................................................................................. i
摘要 ................................................................................................................................ ii
Abstract ............................................................................................................................ iii
圖次 ............................................................................................................................... vi
表次 ............................................................................................................................... ix
第一章 概論 ................................................................................................................... 1
1.1 前言 .............................................................................................................. 1
1.2 研究動機 ...................................................................................................... 5
1.2.1 快速IgE感測系統之頻移讀取電路 .................................................... 5
1.2.2 唯讀記憶體之直接頻率合成器 ............................................................ 6
1.3 相關文獻與研究討論 .................................................................................. 8
1.3.1 適用於FPW感測晶片之濃度偵測電路 .............................................. 8
1.3.2 使用內插法之ROM-less DDFS ........................................................... 9
1.4 論文大綱 .................................................................................................... 12
第二章 快速IgE感測系統之頻移讀取電路 .............................................................. 13
2.1 簡介 ............................................................................................................ 13
2.1.1 頻移讀取系統 ...................................................................................... 13
2.2 讀取電路系統 ............................................................................................ 14
2.3 頻移讀取電路設計 .................................................................................... 16
2.3.1 控制電路 .............................................................................................. 16
2.3.2 頻移讀取電路之數位類比轉換器 ...................................................... 17
2.3.3 頻移讀取電路之偏壓電路 .................................................................. 19
2.3.4 頻移讀取電路之電壓頻率轉換器 ...................................................... 20
2.3.5 頻移讀取電路之運算放大器 .............................................................. 23
2.3.6 頻移讀取電路之減法器 ...................................................................... 24
2.4 頻移讀取電路模擬與分析 ........................................................................ 26
2.5 晶片實作 .................................................................................................... 30
2.6 晶片量測與討論 ........................................................................................ 31
2.6.1 晶片量測結果與分析 .......................................................................... 31
2.6.2 預計規格與實測結果 .......................................................................... 38
第三章 快速IgE感測系統之利用非均分拋物線內插法所實現之無唯讀記憶
體直接頻率合成器 ......................................................................................... 39
3.1 簡介 ............................................................................................................ 39
3.2 非均分式DDFS方法與架構 .................................................................... 41
3.2.1 DDFS架構 ........................................................................................... 42
3.2.2 相位位元長度 ...................................................................................... 44
3.2.3 相位振幅轉換方法 .............................................................................. 45
3.3 電路實現與規格 ........................................................................................ 47
3.4 模擬、FPGA驗證與分析 ......................................................................... 49
3.4.1 非均分式DDFS模擬結果 .................................................................. 49
3.4.2 非均分式DDFS以FPGA驗證結果 .................................................. 50
3.4.3 非均分式DDFS驗證及模擬結果分析 .............................................. 52
第四章 結論、成果與未來工作 ................................................................................. 54
參考文獻 ........................................................................................................................ 57

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