本論文包含兩個主題：應用於家用節能系統之2.45 GHz ZigBee接收器前端與應用於電池管理系統之具固定轉導放大器之三角積分類比數位轉換器。

第一個主題探討應用於家庭節能系統之2.45 GHz ZigBee接收器前端，可在佈線不易之處取代有線通訊系統。本接收器設計提出了一低雜訊放大器，其增益於2.45 GHz時達17.376 dB，以及一含電流分流電晶體的雙平衡式吉伯特混波器，其雜訊指數為5.074 dB，而其三階截點為-7.234 dB。為了降低接收器的相位雜訊，採用了一個低相位雜訊之頻率合成器以及壓控振盪器，其相位雜訊達-137.7 dBc/Hz。本設計並以TSMC 0.18 μm CMOS製程實現並量測效能。

第二個主題為可應用於電池管理系統之具固定轉導放大器之三角積分類比數位轉換器，可應用於電池管理系統中的電池電壓偵測電路。本設計中提出一固定轉導放大器，可解決放大器非線性直流增益影響三角積分調變器性能的問題。此三角積分類比數位轉換器，前級為二階三角積分調變器，在訊號頻寬4 KHz、取樣頻率512 KHz與超取樣率128倍的情況下，SNR達85.2 dB，並具有12位元解析度。後級為數位降頻濾波器，將超取樣頻率降回奈奎氏取樣率(Nyquist rate)並輸出數位值，此數位降頻濾波器以Verilog硬體描述語言撰寫，使用FPGA驗證後，以混合訊號流程整合為一單晶片，並以以TSMC 0.25 μm 60V HV CMOS製程實現。

This thesis consists of two topics: A 2.45 GHz ZigBee Receiver Frontend design for home energy-saving systems and a Delta-Sigma ADC with constant-gm amplifier for Battery Management Systems (BMS).
A 2.45 GHz ZigBee Receiver Frontend for home energy-saving systems is pre-sented in the first part of this thesis. The proposed ZigBee receiver can be used in areas where wireline solutions are hard to be realized. By employing an LNA at the very frontend of the receiver, the gain is simulated to be 17.376 dB at 2.45 GHz. Besides, by using the double-balanced Gilbert mixer with a current bleeding MOS transistor, the NF and the IIP3 of the mixer are only 5.074 dB and -7.234 dB, respectively. To reduce the phase noise of the receiver, a fractional-N frequency synthesizer with a complementary cross-coupled VCO is adopted. The phase noise of the fractional-N frequency synthe-sizer is 137.7 dBc/Hz. The proposed circuit is carried out and measured on silicon using the standard TSMC 0.18 μm CMOS process.
In the second topic, a Delta-Sigma ADC with constant-gm amplifier is presented. The proposed ADC is particularly designed for the voltage detection circuit in BMS. A constant-gm amplifier is also presented to resolve the nonlinearity of the amplifier de-grading the performance of Delta-Sigma modulator, which is the frontend of the Del-ta-Sigma ADC. With the 4 KHz signal bandwidth, 512 KHz sampling frequency, and 128 oversampling rate, it shows a 85.2 dB SNR, and 12-bit resolution. The backend of the ADC is the decimator, which reduces the sampling frequency compliant with the Nyquist rate rule. The decimator is realized by Verilog code and verified by FPGA. By following the mixed-signal flow, the ADC is realized on a single chip using the standard TSMC 0.25 μm 60V HV CMOS process.

致謝 i
摘要 ii
Abstract iii
圖目錄 vii
表目錄 x
第一章 概論 1
1.1 前言 1
1.2 相關文獻與研究探討 5
1.2.1 ZigBee接收器之技術與文獻探討 5
1.2.2 三角積分類比數位轉換器之技術與文獻探討 8
1.3 研究動機 9
1.4 論文大綱 10
第二章 應用於節能系統之2.45 GHz ZigBee接收器前端電路 11
2.1 簡介 11
2.2 ZigBee Rx設計考量 12
2.3 ZigBee Rx電路架構 15
2.4 ZigBee Rx電路設計 16
2.4.1 低雜訊放大器 16
2.4.2 混波器 18
2.4.3 本地端振盪器 21
2.4.4 多相位濾波器 21
2.4.5 雙端轉單端放大器 22
2.4.6 多重回授濾波器 23
2.4.7 可變增益放大器 24
2.5 ZigBee Rx電路模擬與預計規格 25
2.5.1 電路模擬結果 25
2.5.2 預計規格與效能比較 31
2.6 晶片佈局 33
2.6.1 佈局平面圖 33
2.7 晶片實作與量測結果 34
第三章 具固定轉導放大器之三角積分類比數位轉換器 37
3.1 簡介 37
3.2 三角積分類比數位轉換器電路架構 37
3.3 三角積分類比數位轉換器電路設計 39
3.3.1 三角積分調變器 39
3.3.2 切換電容式積分器 40
3.3.3 固定轉導放大器 43
3.3.4 比較器 44
3.3.5 數位類比轉換器 45
3.3.6 時脈訊號產生器 46
3.3.7 數位降頻濾波器 47
3.3.8 偏壓電路 47
3.4 電路模擬與預計規格 49
3.4.1 三角積分類比數位轉換器電路模擬結果 49
3.4.2 預計規格與效能比較 53
3.5 晶片佈局 55
3.5.1 佈局平面圖 55
3.5.2 佈局考量 56
3.6 晶片實作與量測結果 57
第四章 研究成果與結論 60
參考文獻 63

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