本論文提出一個一次性植入式脊髓電刺激系統雛型，本系統運用單一線圈組以電磁感應方式達到無線功率傳輸與雙向資訊傳輸技術之功能。為了延長本植入式脊髓電刺激裝置於人體內之運作時間，以減少傳統植入式裝置因電池耗盡的置換手術次數，本研究運用無線感應充電技術將過剩之能量儲存於鋰電池中。另外，本研究藉由積體電路技術開發一控制晶片，並與晶片外之離散元件組成電路整合至同一印刷電路板上，使植入式裝置體積與目前市售之脊髓電刺激器得以競爭。在功率消耗部分，本控制晶片採雙電壓源架構，以延長鋰電池之使用時間。

本脊髓電刺激系統採用振幅鍵移調變技術進行資料調變與能量傳遞，為了達到較佳之能量傳輸效率，因此對於調變震盪頻率精準度需求較高。為此，本研究開發過程中，因為系統需求而提出一無唯讀記憶體之直接數位頻率合成器以提供高精度之頻率輸出。

考量在印刷電路板上採用之離散元件包含其他市售晶片，在供應電壓方面往往不一致，這會造成不同之輸出入電壓準位，迫使所開發之晶片需要重新設計以符合晶片外部不同電路間之電壓需求，或是在晶片與晶片外部電路之間加上電壓準位轉換器，因此造成大量的面積與成本浪費。為此，本研究提出一具有多重電壓相容之輸出入緩衝器，以單一緩衝器來解決不同電路間之電壓共容問題。

A prototype of a one-time implantable spinal cord stimulation (SCS) system is presented in this thesis. A pair of inductive coils is used to achieve wireless power transmission and bidirectional communication. A rechargeable Li-ion battery is used to extend the lifetime of the implanted SCS device. Therefore, the number of the battery replacement surgery could be reduced such that one-time implantation is feasible. Besides, the proposed system on chip (SOC) controller and many discretes are integrated on a printed circuit board (PCB). The size of the proposed SCS device is competitive compared to the currently commercial products. The proposed SOC controller adopts a dual supply voltage scheme to reduce power consumption.

The proposed SCS system employs an amplitude-shift keying (ASK) technique to carry out the data modulation and power transmission. One of the critical factors to affect efficiency of ASK-based wireless power transmission is the oscillating frequency accuracy. A ROM-less direct digital frequency synthesizer (DDFS) is presented in this thesis to fulfill such a high accuracy demand.

Since the supply voltages of the discretes are diversified on a system PCB, many level converters are needed to translate different signal output voltage levels. To resolve above problem, the chip, then, must be redesigned to meet the various voltage level requirement, or added level convertors among the SOC and the discretes. Obviously, it will cause a lot of cost. A wide-range I/O buffer, thus, is proposed to resolve the compatibility problem caused by different supply voltages of discretes.

論文審定書i
誌謝iii
中文摘要iv
Abstract v
List of Figures ix
List of Tables xii
Chapter 1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Literature Review . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.1 Gate Control Theory . . . . . . . . . . . . . . . . . . . . . . . 3
1.2.2 Spinal Cord Stimulation . . . . . . . . . . . . . . . . . . . . . 6
1.2.3 Direct Digital Frequency Synthesizer . . . . . . . . . . . . . . 10
1.2.4 I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.3 Organization of the Thesis . . . . . . . . . . . . . . . . . . . . . . . . 19
Chapter 2 One-time Implantable Spinal Cord Stimulation System 20
2.1 Chapter Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
2.2 Architecture of the Proposed SCS System . . . . . . . . . . . . . . . . 21
2.2.1 External Module . . . . . . . . . . . . . . . . . . . . . . . . . 23
2.2.2 Internal Module . . . . . . . . . . . . . . . . . . . . . . . . . . 27
2.3 Implementation and Measurement . . . . . . . . . . . . . . . . . . . . 38
2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Chapter 3 ROM-less DDFS Using Parabolic Polynomial Interpolation Method 48
3.1 Chapter Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
3.2 Parabolic Polynomial Interpolation Methods . . . . . . . . . . . . . . 49
3.3 Architecture of the Proposed ROM-less DDFS . . . . . . . . . . . . . 50
3.3.1 Parabolic Polynomial Interpolation . . . . . . . . . . . . . . . 50
3.3.2 Iterative Derivation of Offsets . . . . . . . . . . . . . . . . . . 51
3.3.3 Performance Evaluation . . . . . . . . . . . . . . . . . . . . . 52
3.3.4 Hardware Implementation . . . . . . . . . . . . . . . . . . . . 55
3.4 Implementation and Measurement . . . . . . . . . . . . . . . . . . . . 57
3.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Chapter 4 A 1/2 x VDD to 3 x VDD Bidirectional I/O Buffer With A Dynamic Gate Bias Generator 62
4.1 Chapter Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
4.2 1/2 x VDD to 3 x VDD Bidirectional I/O Buffer . . . . . . . . . . . . . . 63
4.2.1 Pre-driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4.2.2 High voltage detector . . . . . . . . . . . . . . . . . . . . . . . 65
4.2.3 Dynamic gate bias generator . . . . . . . . . . . . . . . . . . . 67
4.2.4 PAD voltage detector . . . . . . . . . . . . . . . . . . . . . . . 76
4.2.5 Output stage . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
4.2.6 Floating N-well circuit . . . . . . . . . . . . . . . . . . . . . . 78
4.2.7 Gate-tracking circuit . . . . . . . . . . . . . . . . . . . . . . . 79
4.2.8 Input stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
4.3 Implementation and Measurement . . . . . . . . . . . . . . . . . . . . 81
4.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Chapter 5 Conclusion and Future Works 91
5.1 Conclusion and Contribution . . . . . . . . . . . . . . . . . . . . . . . 91
5.2 Future Works . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Bibliography 94

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