現今電腦系統，運作速度已由數百MHz提升至GHz頻段，當邏輯閘快速切換時，瞬間的電流變化會經由IC接腳，傳至主機板電源供應平面，造成電源面電壓波動之現象，稱為「接地彈跳(Ground bounce)」。為防止接地彈跳造成主機板上IC判斷錯誤，可使用解耦合電容加以防制，本論文運用二維時域有限差分法(2D FDTD)，配合一種單網格計算RLC串聯之遞迴演算法，以快速模擬具解耦合電容之電源供應平面；同時，加入Debye model、FDTD-SPICE、及telegrapher’s equation之方法，使此二維模型可廣泛應用至多層板及具槽孔之主機板結構，並可考慮FR4介質之色散效應。最後，為提供配置解耦合電容之有效方式，使用基因演算法，搭配已建立的二維模擬模型，來計算出符合期望目標之電容擺放方法。

The operation speed of modern computer system has been upgraded from several hundred MHz to GHz. The instant current will pass to the power plane of the mother board by way of the IC pins and result in electromagnetic wave propagation between the power and ground plane, so called “Ground bounce.” To prevent the ground bounce from IC operation, decoupling capacitors are used. In this thesis, an efficient numerical approach which is based on the two-dimensional (2D) finite-difference time-domain (FDTD) method and with a new recursive algorithm has been used for modeling the power/ground planes characteristics with SMT capacitors above them. By the way, we take several methods, such as Debye model, FDTD-SPICE, and telegrapher’s equation, for modeling various mother board structures. Finally, we use the genetic algorithm for calculating the optimum capacitor placements to meet the expect ground bounce limitation.

目錄
圖表索引
第一章 序 1
1.1 研究目的與方法 1
1.2 論文大綱 5
第二章 FDTD演算法 6
2.1 馬克斯威爾方程式 6
2.2 三維方程式 6
2.2.1 中央差分與Yee網格配置 7
2.2.2 邊界條件 9
2.3 二維方程式 10
2.3.1 TMz模態之中央差分與網格配置 11
2.3.2 TMz模態之邊界條件 12
2.4 網格大小與穩定準則 13
2.5 集總元件 13
2.5.1 電阻 14
2.5.2 電感 15
2.5.3 電容 15
2.5.4 阻抗性電壓源 15
2.6 程式執行流程 16
第三章 單網格RLC串聯與FR4介質色散 17
3.1 結構及問題描述 17
3.1.1 測試結構I.－裸板 17
3.1.2 測試結構II.－加電容 18
3.1.3 問題討論與改進方向 19
3.2 單網格RLC串聯方法 22
3.2.1 演算法推導 22
3.2.2 模擬結果 26
A. 1顆電容 26
B. 2∼4顆電容 27
C. 結果討論 29
3.3 FR4色散介質 30
3.3.1 Debye media 30
3.3.2 片段線性遞迴迴旋積法(PLRC Method) 31
3.3.3 具Debye model之FDTD演算法 32
3.3.4 模擬結果 33
A. 測試板裸板 33
B. 1顆電容 33
C. 2∼4顆電容 34
D. 結果討論 35
3.4 模型深入驗證 36
第四章 多層板之模擬 38
4.1 結構及模擬方法 38
4.1.1 具封裝結構之PCB 38
4.1.2 以2D FDTD及FDTD-SPICE模擬四層板 39
4.2 FDTD-SPICE 40
4.2.1 等效電流源法 40
4.2.2 牛頓法逼近 41
4.3 模擬與量測結果 42
4.3.1 具封裝結構之PCB－連通柱對數探討 42
A. 1對連通柱 42
B. 2對連通柱 42
C. 4對及8對連通柱 44
D. 連通柱對數對|S21|之影響 44
4.3.2 具封裝結構之PCB－加SMT解耦合電容 45
第五章 微帶線及槽孔之模擬 49
5.1 問題描述 49
5.2 一維方式之微帶線模擬 49
5.2.1 電報方程式 49
5.2.2 輸入端與輸出端 51
A. 輸入端－戴維寧式阻抗性電壓源 51
B. 輸入端－諾頓式阻抗性電流源 51
C. 輸出端－負載電阻 52
5.2.3 微帶線模擬結果 53
5.3 電報方程式與2D FDTD之結合 54
5.3.1 微帶線 55
5.3.2 槽線電源供應平面 55
A. 以一維及二維模擬之模型 55
B. 修正式推導 56
C. 開槽轉角修正 58
5.4 模擬結果 59
A. 微帶線跨越槽孔 59
B. 開槽對接地彈跳之影響－單一開槽 60
C. 開槽對接地彈跳之影響－L字型開槽 61
D. 開槽對接地彈跳之影響－U字型開槽 62
E. 開槽對接地彈跳之影響－開槽完全隔離激發源 63
第六章 以基因演算法考慮電容位置 65
6.1 量測情形與實驗目的 65
6.2 基因演算法 66
6.2.1 計算流程 66
A. 編碼(Coding) 67
B. 初始族群(Initial population) 68
C. 適應函數(Fitness function) 68
D. 選擇策略(Selection strategy) 68
E. 遺傳運算元(Operator) 69
F. 停止規則 70
6.2.2 簡單演算例 70
6.3 基因演算法與2D FDTD計算電容位置 71
6.3.1 計算流程 71
6.3.2 計算結果 73
A. 測試I－擺放3顆電容 73
B. 測試結構II－擺放10顆電容 74
6.3.3 討論與說明 74
第七章 結論 76
參考文獻 78

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