渦輪碼(Turbo Code)，由於它提供了優越的錯誤更正能力，所以近年來被廣泛的運用在許多新穎的無線通訊系統以及資料儲存系統之中。然而，由於渦輪碼需要尋找所有狀態點的機率(Probability)以及尋找傳輸序列，這需要大量的記憶體空間以及複雜的記憶體控制，使得渦輪碼硬體的實現並不是這麼容易。
　　在本論文中，提出了一個可參數化碼率(code rate)以及位元寬度的渦輪碼解碼器數位矽智產(Intellectual Property，IP)，渦輪碼解碼器核心單元SISO(Soft-In Soft-Out)是根據軟輸出腓持比演算法(SOVA)來設計。根據混合式向後追溯法則(hybrid trace-back scheme)，在論文中所採用的SISO單元可達到更快的路徑搜尋，且儲存路徑的記憶體相較於傳統的向後追溯法(trace-back)也減少了70 %。另外，渦輪碼解碼器在每次的遞迴解碼需執行兩組的SISO單元來對正常資料區塊以及交錯(interleaving)後的資料區塊做運算，在本論文中所採用的架構，僅使用一個SISO單元來實現兩個SISO的運算，減少了多餘的控制。接著在渦輪碼解碼器的設計中也採用了Threshold和Normalization技巧來改善位元錯誤率(bit error rate)的效能。另外，在解碼器的設計之中也加入了遞迴停止機制(Termination criteria)電路來降低解碼時所需要的遞迴(iteration)週期次數。
　　本論文中所介紹的渦輪碼解碼器已經過完整測試及驗證，因此可成為一個可靠且實用的數位矽智產。

Turbo Code, due to its excellent error correction capability, has been widely used in many modern wireless digital communication systems as well as data storage systems in recent years. However, because the decoding of the Turbo Code involves finding all the state probability and transition sequence, its hardware implementation is not straightforward as it requires a lot of memory and memory operation. In this thesis, a design of Turbo Code decoder IP (Intellectual Property) is proposed which can be parameterized with different word-lengths and code rates. The design of the core SISO (Soft-In Soft-Out) unit used in Turbo Code decoder is based on the algorithm of SOVA (Soft-Output Viterbi Algorithm). Based on the hybrid trace-back scheme, the SISO proposed in this thesis can achieve fast path searching and path memory reduction which can be up to 70% compared with the traditional trace-back approach. In addition, every iterative of Turbo Code decoding performs two SISO operations on the block of data with normal and interleaving order. In our proposed architecture, these two SISO operations can be implemented on a single SISO unit with only slightly control overhead. In order to improve the bit error rate performance, the threshold and normalization techniques are applied to our design. In addition, the termination criteria circuit is also included in our design such that the iteration cycle of the decoding can be reduced. The proposed Turbo Code decoder has been thoroughly tested and verified, and can be qualified as a robust IP.

Chapter 1. Introduction
1.1 Background and motivation
1.2 Scope of the thesis

Chapter 2. Two-Step SOVA
2.1 Two-Step SOVA architecture
2.2 Design of Two-Step SOVA
2.2.1 BMU (Branch Metric Unit)
2.2.2 ACSU (Add-Compare-select Unit)
2.2.3 SMU (Survivor path Memory Unit)
2.2.4 PCU (Path Comparison Unit)
2.2.5 RMU (Reliability Measure Unit)

Chapter 3. Turbo Code
3.1 Turbo Code Encoder
3.1.1 Convolutional Encoder
3.1.2 Recursive Systematic Convolutional (RSC) Encoder
3.1.3 Trellis Termination
3.2 Turbo Code decoder
3.3 Implementation and improvement of Turbo Code
3.3.1 Interleave and De-interleave
3.3.2 Threshold and normalization
3.3.3 Termination criterion
3.4 Performance Comparison

Chapter 4. IP builder
4.1 Key features and claims
4.2 Configuration information and parameters
4.2.1 System parameters
4.2.2 Configurable parameters
4.2.3 Programmable parameters
4.3 Comprehensive technical specification and data sheet
4.4 Application method of the IP
4.5 Provided design models
4.5.1 Reference model
4.5.2 RTL Model
4.5.3 Gate Level Model
4.6 Verification strategy
4.6.1 Functional Verification
4.6.2 Coding Style Checking
4.6.3 Code Coverage Testing
4.6.4 Gate-Level Verification
4.7 Test plan/methods and testability measurement
4.7.1 Random case Testing
4.7.2 Corner case Testing
4.7.3 FPGA Prototyping with BIST mode

Chapter 5. Conclusion
References

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