近年來，電子產品包含顯示器面板，記憶體，以及可攜式產品等等，都變得愈來愈受消費展歡迎。而這些電子產品絕大部分都包含有金氧半場效電晶體(Metal-Oxide-Semiconductor Field Effect Transistors, MOSFETs)。這是由於比起其他電晶體，它具有較低的製造成本、較低的功率消耗、以及它很容易微縮。
然而，在傳統電晶體持續的微縮後，會面臨閘極漏電，短通道效應…等問題，這不但會降低閘極的控制能力，還會增加元件的功率消耗。為了解決這些問題，因此使用了矽覆絕緣(silicon on insulator, SOI)，與高介電常數氧化層/金屬閘極(high-k/metal gate)堆疊結構和鰭式之金氧半場效電晶體(Fin Field Effect Transistors, FinFETs)。
因此，本論文會針對n型的SOI MOSFETs以及FinFETs兩種元件，去做電性分析以及熱載子應力(hot carrier stress, HCS)和正偏壓應力(positive bias stress, PBS)的探討。本論文可依元件結構而粗分成部分空乏(partially depleted, PD)矽覆絕緣金氧半場效電晶體和鰭式電晶體兩大部分。
在PD SOI MOSFETs這個部分，我們分成三個小節來探討其電性以及熱載子應力劣化的物理機制。第一小節探討的是PD SOI的浮體效應對變溫的熱載子應力之影響。實驗結果顯示，在相同熱載子應力的條件下，在基板不接(floating body, FB)操作下的劣化會比基板接地(body contact, BC)操作下的劣化嚴重。經由快速量測的實驗驗證後，發現這是由於碰撞遊離後的電洞累積在基板，而造成浮體效應所導致的。接著，我們也討論了FB操作下，在不同溫度時的熱載子應力的劣化比較。實驗結果顯示，在FB操作下的熱載子應力劣化，會隨著溫度上升，而變得愈來愈不嚴重。經過一系列的實驗去驗證後，發現FB操作下的變溫熱載子應力劣化為源極/汲極和基板間的PN接面(PN junction)可儲存電洞的能力所主導。
在第二小節中，我們在發現PDSOI基底接觸結構(body contact structure)中發現，有一個異常第二個的轉導峰值存在，但是在沒有PDSOI基底接觸結構中，卻未發現此現象。我們認為是由於，這個元件是使用L型閘極(L-Gate)的基底接觸結構，因此有部分的閘極是P型的，使得元件出現一個寄生通道的現象。利用不同的量測手法和可靠度研究，可證明我們提出的模型。
在SOI的最後一個小節中，我們使用的元件結構為 PD SOI Lateral diffusion (LD) MOSFETs。相較於一般的熱載子應力劣化，只跟汲極工程最為相關，但在這邊卻發現，resist protected oxide (RPO)的品質竟然會顯著的影響熱載子應力的劣化程度。經由ISE-TCAD軟體的電性模擬之後可知道，碰撞游離最嚴重的地方會發生在，低N型參雜的耐壓區(N- drift region)和N+汲極的介面，而且在此處的電場方向是指向RPO的，因此在熱載子應力施加時，在RPO中，會有明顯的載子注入情況，使得元件在熱載子應力後的電性受到影響。
而在鰭式之金氧半場效電晶體之研究中，我們也去針對它的電性以及可靠度去做物理機制的探討。
ㄧ般而言，在飽和區量測下，才會出現基底電流，這是由於碰撞游離，使得在靠近汲極的地方有電子電洞對的產生。很有趣的是，在本研究中發現，線性區竟然出現了ㄧ個異常的基底電流。我們猜測這個異常的基底電流是因為Fin形成時，會經過很多道的蝕刻步驟，因此Fin的表面有許多的介面缺陷，而這些介面缺陷就是導致異常基底電流的主因。最後，我們去量測不同汲極偏壓下的異常基底電流，變溫的基底電流量測，以及改變通道長度的基底電流量測，這些都證明了我們所提出的模型。
最後，我們也研究了，在鰭式電晶體中的，不同通道長度的元件，對於正偏壓應力的影響。由於PBS的實驗，是指有施加閘極偏壓的，所以應該和元件的通道長度沒有關係。但實驗結果卻指出，長通道元件中的PBS劣化，比短通道元件還要嚴重。更特別的是，在短通道的PBS後，竟然看到了一個異常的轉導峰值上升情形。由ISE-TCAD軟體的電場模擬可知，這是由於在沿著Fin寬方向的中間，在通道方向的邊緣處，有一強電場，使得電洞會從閘極往閘極絕緣層注入，導致電子聚積在靠近LDD處，因此降低了有效通道的長度。又由於通道縮短的長度是一樣的，因此，這個現象在短通道元件中會顯得更為顯著。

Recently, electronic products combining display panels, memory devices, and portable devices have become more popular for consumers. These electronic products are mostly composed of metal-oxide-semiconductor field effect transistors (MOSFETs). It is due to MOSFETs having the advantage of low cost, low power consumption and the ability to be scaled down easily. However, continuous scaling down of traditional MOSFETs can face problems like, gate leakage, short channel effect…etc. It not only reduces gate control ability but also increases device power consumption. To solve these problems, silicon on insulator, (SOI), high-k/metal gate stack structure, and Fin Field Effect Transistors (FinFETs) have been used. Therefore, in this dissertation, we will focus on n-type MOSFETs and FinFETs devices to investigate electrical characteristics, hot carrier stress (HCS), and positive bias stress (PBS). This dissertation can be roughly divided into two parts based on device structure. One is partially depleted silicon on insulator, (PD-SOI) and the other is FinFETs.
The PD SOI MOSFETs section is divided into three sections to investigate the physical mechanisms and hot carrier degradation. The first PD SOI section, we investigates the behavior of hot carrier-induced degradation at different temperatures under GB and FB operations, and finds that the degradation under FB is more serious than that under GB operation due to the floating body effect. Fast I–V shows a drain current rise after FB-HCS. This can be attributed to the fact that impact-ionization-generated holes are injected into the floating substrate. Next experience with hot carrier stress degradation with different temperature, and find the degradation under FB operation becomes less significant with increasing temperature. This is due to the lessened ability to retain holes at the source/body PN junction at high temperature and the resultant insignificant FBE. According to this study, hot-carrier-induced degradation under GB operation at different temperatures is dominated by the impact ionization rate, while the degree of degradation under FB operation is dominated by the ability to retain holes at the source/body PN junction.
In the second PD-SOI section, founded and investigated abnormal charge pumping current (ICP) in body-tied partially-depleted silicon-on-insulator n-channel metal-oxide-semiconductor field effect transistors. The ICP second hump region increases with channel length, yet is not affected by channel width in the L-gate structure. Because of a part of the poly gate area near the body contact is covered by a P+ implant, inducing a parasitic channel under the P+ poly gate. This parasitic channel leads to the abnormal Gm and ICP hump, and such mechanism is further verified by different measurement and reliability methods.
In the second PD-SOI section, we investigates the origin of an anomalous enhancement in on-state current under hot carrier stress and temperature dependent hot-carrier-induced degradation in lateral diffused SOI n-MOSFETs. Threshold voltage and subthreshold swing degrade, whereas an abnormal on-state current exhibits a quick rise after HCS due to hole trapping in the resist-protective oxide. Impact ionization simulation shows that low doping concentrations in the drift region causes a severe Kirk effect under HCS and more severe degradation at higher VG. Notably, degradation in the channel contrasts with the simulation result, which suggests another mechanism. Moreover, variable temperature HCS verifies that channel degradation is dominated by temperature.
Finally, in the high-k/metal gate stack FinFETs section, we also investigated electrical characteristics and reliability. The first section in FinFETs, we investigates the mechanism of abnormal body current at the linear region in n-channel high-k/metal gate stack FinFETs. Unlike body current, which is generated by impact ionization at high drain voltages, abnormal body current was found to increase with decreasing drain voltages. Notably, the unusual body leakage only occurs in three-dimensional structure devices. Based on measurements under different operation conditions, the abnormal body current can be attributed to fin surface defect-induced leakage current, and the mechanism is electron tunneling to the fin via the defects, resulting in holes left at the body terminal.
In the second section of FinFETs, we investigate an abnormal transconductance (Gm) enhancement after positive bias stress (PBS) in n-channel HK/MG FinFETs. This abnormal Gm enhancement after PBS is observed only in short channel devices. With the speculation that hole-trapping-induced electron accumulation is the dominant mechanism, PBS with floating source and drain is adopted as an investigative approach. This, together with the electric field simulation, verifies that hole-trapping in the HfO2 and SiN near the gate corner induces electron accumulated at the ends of the channel length. Such a phenomenon results in a shortening of effective channel length and further Gm enhancement

[ 摘要 ii ]
[ Abstract vi ]
[ Figure Captions xiv ]
[ Chapter 1 1 ]
[ 1.1 Basic Background 1 ]
[ 1.1.1 Overview of Moore’s Law, Roadmap of scaling down 1 ]
[ 1.1.2 Overview of Silicon-on-Insulator (SOI) MOSFETs 3 ]
[ 1.1.3 Overview of high-k/metal gate MOSFETs 4 ]
[ 1.1.4 Overview of FinFETs 5 ]
[ Reference 7 ]
[ Chapter 2 Parameter Extraction and Measurement Technique 20 ]
[ 2.1 Method of Device Parameter Extraction 20 ]
[ 2.1.1 Determination of threshold voltage (VT) 20 ]
[ 2.1.2 Determination of the subthreshold swing 21 ]
[ Reference 22 ]
[ Chapter 3 27 ]
[ 3.1 Introduction 28 ]
[ 3.2 Experiment 29 ]
[ 3.3 Result and Discussion 29 ]
[ 3.4 Summary 35 ]
[ Reference 36 ]
[ Chapter 4 53 ]
[ 4.1 Introduction 53 ]
[ 4.2 Experiment 54 ]
[ 4.3 Result and Discussion 55 ]
[ 4.4 Summary 58 ]
[ Reference 59 ]
[ Chapter 5 70 ]
[ 5.1 Introduction 71 ]
[ 5.2 Experiment 72 ]
[ 5.3 Result and Discussion 73 ]
[ 5.4 Summary 80 ]
[ Reference 82 ]
[ Chapter 6 99 ]
[ 6.1 Introduction 99 ]
[ 6.2 Experiment 100 ]
[ 6.3 Result and Discussion 101 ]
[ 6.4 Summary 104 ]
[ Reference 106 ]
[ Chapter 7 120 ]
[ 7.1 Introduction 120 ]
[ 7.2 Experiment 122 ]
[ 7.3 Result and Discussion 123 ]
[ 7.4 Summary 127 ]
[ Reference 128 ]
[ Chapter 8 141 ]
[ Publication List 145 ]
[ Vita 簡 歷 150 ]

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