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博碩士論文 etd-0708116-115616 詳細資訊
Title page for etd-0708116-115616
論文名稱
Title
氧氣電漿表面處理對具氮化鈦/二氧化鉿閘極堆疊之N型多晶矽薄膜電晶體的性能與可靠度影響之研究
Impacts of Oxygen Plasma Surface Treatment on Performance and Reliability of N-type Poly-Si Thin-Film Transistors With TiN/HfO2 Gate Stack
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
62
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2016-07-15
繳交日期
Date of Submission
2016-08-08
關鍵字
Keywords
可靠度、氧氣電漿表面處理、多晶矽薄膜電晶體、高介電常數閘極介電質、短通道效應
O2 plasma surface treatment, poly-Si TFTs, high-k gate dielectric, short channel effect, reliability
統計
Statistics
本論文已被瀏覽 5745 次,被下載 47
The thesis/dissertation has been browsed 5745 times, has been downloaded 47 times.
中文摘要
多晶矽薄膜電晶體在主動型液晶螢幕中的應用是其技術不斷發展的主要推動力,傳統的以二氧化矽作為介電質的多晶矽薄膜電晶體尺寸不斷微縮,但已逐漸不能滿足高性能的需求。
高介電常數之閘極介電質可以提升閘極電容密度,吸引更多載子,提升元件特性。其中二氧化鉿作為高介電常數之閘極介電質材料的發展頗有前景。同時矽通道的晶粒邊界存在著缺陷,這些缺陷會捕捉載子形成能障,影響元件性能。氧氣電漿表面處理可以鈍化這些缺陷並改善閘極氧化層與多晶矽介面的品質。
本文對經過氧氣電漿表面處理以及未經過氧氣電漿表面處理的具氮化鈦/二氧化鉿閘極堆疊之N型多晶矽薄膜電晶體進行對比量測:
為研究氧氣電漿表面處理對具氮化鈦/二氧化鉿閘極堆疊之N型多晶矽薄膜電晶體的性能之影響,在室溫下,量測通道寬度為100μm,通道長度分別為20μm、10μm、5μm、2μm、1μm的N型多晶矽薄膜電晶體的轉移特性和輸出特性;對於各個通道長度,經過氧氣電漿表面處理的N型TFT的電性都得到了提升。
為研究氧氣電漿表面處理對具氮化鈦/二氧化鉿閘極堆疊之N型多晶矽薄膜電晶體的可靠度之影響,對於通道寬長比為100μm /10μm的N型多晶矽薄膜電晶體,測量其125℃下的正向偏壓劣化特性,施加於閘極的偏壓分別滿足VOV=VG-VTH=5V,6V,7V,施加的偏壓使元件的性能劣化,而氧氣電漿表面處理減小了其劣化程度,提高了元件的可靠度。
Abstract
The application of polysilicon thin-film transistors in active matrix liquid crystal displays has been the main driver of the development of polysilicon thin-film transistors technology. The conventional poly-Si TFTs with SiO2 gate dielectric has been scaling down to meet the requirements of high performance, but hard to achieve this goal.
Using high-κ materials as gate dielectric layer can improve gate capacitance density and induce more carriers to enhance the device characteristics. Among the high-κ materials, HfO2 is a promising alternative to be the gate dielectric. On the other side, there could be defects in the grain boundary of poly-Si channel film, which would capture carriers to form potential barrier and affect device performance. Oxygen plasma surface treatment is capable of passivating these defects and improving the gate dielectric/poly-Si interface quality.
In this paper, impacts of oxygen plasma surface treatment on performance and reliability of n-type poly-Si thin-film transistors with TiN/HfO2 gate stack have been researched:
To study the impact of oxygen plasma surface treatment on performance of n-type poly-Si thin-film transistors with TiN/HfO2 gate stack, measurements of the transfer characteristics and output characteristics have been performed on HfO2 poly-Si N-type TFTs of various channel length without and with O2 plasma surface treatment at room temperature. Enhancement of device performance has been observed through all the channel length of 20μm, 10μm, 5μm, 2μm and 1μm with O2 plasma surface treatment.
To study the impact of oxygen plasma surface treatment on reliability of n-type poly-Si thin-film transistors with TiN/HfO2 gate stack, measurements of the transfer characteristics and output characteristics have been performed on HfO2 poly-Si N-type TFTs of W/L = 100m/10m without and with O2 plasma surface treatment at the temperature of 125℃, the PBTI stress condition being set as VOC = VG-VTH = 5V, 6V, 7V. The PBTI degradation characteristics have been observed, while the O2 plasma surface treatment has reduced the degradation and enhanced the device reliability.
目次 Table of Contents
論文審定書 i
致謝 ii
摘要 iii
ABSTRACT iv
目錄 v
圖次 vii
表次 xi
第一章 緒論 1
1.1 多晶矽薄膜電晶體的結構和基本操作 1
1.2 多晶矽薄膜電晶體的漏電流機制 2
1.3 多晶矽薄膜電晶體之缺陷的鈍化 2
1.4 多晶矽薄膜電晶體的短通道效應 3
1.5 高介電常數閘極介電層 3
1.6 多晶矽薄膜電晶體的可靠度 5
第二章 實驗流程 12
2.1 元件性能相關參數的萃取 12
2.1.1 次臨界擺幅 12
2.1.2 臨界電壓 12
2.1.3 載子遷移率 13
2.1.4 電流開關比 13
2.1.5 晶粒邊界陷阱能態密度 13
2.1.6 介面陷阱能態密度 14
2.2 元件製程步驟 14
第三章 結果與討論 24
3.1 氧氣電漿處理對電晶體性能影響之分析 24
3.2 氧氣電漿處理對電晶體可靠度影響之分析 26
3.2.1 不同應力條件下電性隨應力時間的變化 26
3.2.2 電性改變量隨施加應力大小的變化 28
第四章 結論 48
參考文獻 49
參考文獻 References
[1] K. R. Olasupo and M. K. Hatalis, "Leakage Current Mechanism in Sub-Micron Polysilicon Thin-Film Transistors," IEEE Transactions on Electron Devices, vol. 43, no. 8, pp. 1218-1223, Aug. 1996.
[2] I. W. Wu, T. Y. Huang, W. B. Jackson, A. G. Lewis and A. Chiang, "Passivation Kinetics of Two Types of Defects in Polysilicon TFT by Plasma Hydrogenation," IEEE Electron Device Letters, vol. 12, no. 4, pp. 181-183, Apr. 1991.
[3] J. Y.W. Seto, "The Electrical Properties of Polycrystalline Silicon Films," Journal of Applied Physics, vol. 46, no. 12, pp. 5247-5254, Dec. 1975.
[4] G. Baccarani, B. Ricco and G. Spadini, "Transport Properties of Polycrystalline Silicon Films," Journal of Applied Physics, vol. 49, no. 11, pp. 5565-5570, Nov. 1978.
[5] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices, Cambridge University Press, 2013.
[6] C. P. Lin, B. Y. Tsui, M. J. Yang, R. H. Huang and C. H. Chien, "High-Performance Poly-Silicon TFTs Using HfO2 Gate Dielectric," IEEE Electron Device Letters, vol. 27, no. 5, pp. 360-363, May 2006.
[7] H. Xiao, Introduction to Semiconductor Manufacturing Technology, Society of Photo Optical, 2012.
[8] M. W. Ma, T. Y. Chiang, W. C. Wu, T. S. Chao and T. F. Lei, "Characteristics of HfO2/Poly-Si Interfacial Layer on CMOS LTPS-TFTs With HfO2 Gate Dielectric and O2 Plasma Surface Treatment," IEEE Transactions on Electron Devices, vol. 55, no. 12, pp. 3489-3493, Dec. 2008.
[9] M. W. Ma, C. Y. Chen, W. C. Wu, C. J. Su, K. H. Kao, T. S. Chao and T. F. Lei, "Reliability Mechanisms of LTPS-TFT With HfO2 Gate Dielectric: PBTI, NBTI, and Hot-Carrier Stress," IEEE Transactions on Electron Devices, vol. 55, no. 5, pp. 1153-1160, May 2008.
[10] D. A. Neamen, Semiconductor Physics and Devices, McGraw-Hill, Inc., 2002.
[11] J. Levinson, F. R. Shepherd, P. J. Scanlon, W. D. Westwood, G. Este and M. Rider, "Conductivity Behavior in Polycrystalline Semiconductor Thin Film Transistors," Journal of Applied Physics, vol. 53, no. 2, pp. 1193-1202, Feb. 1982.
[12] R. E. Proano, R. S. Misage and D. G. Ast, "Development and Electrical Properties of Undoped Polycrystalline Silicon Thin-Film Transistors," IEEE Transactions on Electron Devices, vol. 36, no. 9, pp. 1915-1922, Sep. 1989.
[13] C. A. Dimitriadis, P. A. Coxon, L. Dozsa, L. Papadimitriou and N. Economou, "Performance of Thin-Film Transistors on Polysilicon Films Grown by Low-Pressure Chemical Vapor Deposition at Various Pressures," IEEE Transactions on Electron Devices, vol. 39, no. 3, pp. 598-606, Mar. 1992.
[14] W. C. Y. Ma, T. Y. Chiang, J. W. Lin and T. S. Chao, "Oxide Thinning and Structure Scaling Down Effect of Low-Temperature Poly-Si Thin-Film Transistors," Journal of Display Technology, vol. 8, no. 1, pp. 12-17, Jan. 2012.
[15] M. W. Ma, C. Y. Chen, C. J. Su, W. C. Wu, Y. H. Wu, K. H. Kao, T. S. Chao and T. F. Lei, "Characteristics of PBTI and Hot Carrier Stress for LTPS-TFT With High-κ Gate Dielectric," IEEE Electron Device Letters, vol. 29, no. 2, pp. 171-173, Feb. 2008.
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