隨著 3D 繪圖技術的發展,為了讓使用者享受更好的畫面和視覺效果,使得處理圖形時所需要的計算也越來越複雜。而在可攜式電子產品中，電池電量是有限的。為了延長電池的續航力並且能夠呈現使用者滿意的畫面，降低硬體消耗的功率以及加速資料運算的速度即成為開發3D 繪圖處理器時很重要的目標。
在 OpenGL ES 3D 繪圖管線中可分為前半部的Geometry Stage 以及後半部的Rasterization Stage。本論文以 ATTILA 模擬器為基礎，實作出具有可變精確度運算模式以及管線化排程之光柵化單元。此外,我們也結合了本實驗室開發的特殊函數運算單元，用以降低原本運算中使用除法器的面積與延遲。在低功率設計方面藉由降低運算資料的精確度，以及減少電路中訊號切換的次數，達到節省功率消耗的效果，最後輸出人眼可接受的失真影像。

With the development of 3D graphics technology, the required computations for processing graphics has become increasingly complex to allow users to enjoy the better image quality and visual effects. But the battery power within the portable electronic products is limited. For the purpose of extending the battery’s endurance and showing the scene that satisfies the user’s requirement, reducing power consumption and accelerating computing speed of the hardware circuit are important features for the portable electronic products today.
The OpenGL ES 3D graphics pipeline can be divided into the former part – Geometry Stage and the latter part – Rasterization Stage. In this thesis, we present a multi-precision rasterizer with pipeline scheduling based on ATTILA simulator. Moreover, we employ the special function unit to reduce the required area and delay for performing the division operations in the design. By degrading the accuracy of the input data to reducing the switching activities of the hardware circuits, we can saven power consumption. In the meantime, the quality of output images is still acceptable.

誌謝 ii
論文提要 iii
摘要 iv
Abstract v
目錄 vi
圖目錄 viii
表目錄 x
第一章 序論 1
1.1 研究動機 1
1.2 論文大綱 3
第二章 研究背景 4
2.1 三維繪圖簡介 4
2.1.1 三維繪圖管線流程（3D Rendering Pipeline） 4
2.1.2 幾何階段（Geometry Stage） 4
2.1.3 光柵化階段（Rasterization Stage） 6
2.2 OpenGL ES簡介 7
2.3 ATTILA三維繪圖模擬器 9
2.3.1 ATTILA模擬器架構 9
2.3.2 Unified Shader架構與指令格式 12
2.3.3 ATTILA驗證流程 14
第三章 光柵化單元功能與演算法 15
3.1 光柵化流程介紹 15
3.2 Triangle Setup 16
3.2.1 Edge Equation 16
3.2.2 Bounding Box 19
3.3 Triangle Traversal 19
3.3.1 Bounding Box Traversal 19
3.3.2 Skip Traversal 20
3.3.3 Zigzag Traversal 20
3.3.4 Hilbert Curve Traversal 21
3.4 Interpolation 24
第四章 提出的光柵化單元架構與設計 25
4.1 整體架構概要 25
4.2 內部硬體模組設計 27
4.2.1 Triangle Setup 27
4.2.2 Triangle Traversal 33
4.2.3 Interpolator 33
4.3 多重精確度設計 35
4.4 特殊函數運算單元 36
4.4.1 Special Function Unit (SFU) Architecture 36
4.4.2 定點數−浮點數格式轉換器 36
4.4.3 浮點數−定點數格式轉換器 37
4.5 管線化排程設計 41
第五章 實驗結果 44
5.1 實驗步驟與方法 44
5.2 除法器與特殊函數運算單元比較 45
5.3多重精確度運算實驗結果 46
5.3.1多重精確度光柵化單元數據分析 47
5.3.2 不同精確度影像之分析 49
第六章 結論與未來研究方向 54
6.1結論 54
6.1未來研究方向 54
參考文獻 55

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[2] Khronos Group: http://www.khronos.org/
[3] ATTILA: http://attila.ac.upc.edu/wiki/index.php/Main_Page
[4] ARB Vertex Program Extension:
http://oss.sgi.com/projects/ogl-sample/registry/ARB/vertex_program.txt
[5] ARB Fragment Program Extension:
http://oss.sgi.com/projects/ogl-sample/registry/ARB/fragment_program.txt
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