這篇論文發表了三個應用於低功率動態隨機存取記憶體（DRAM）的高性能電路。 首先，一個使用輔助傳輸閘與電荷再利用技巧的改善多級感測放大器被提出。 傳輸閘取代了多級感測放大器中輔助的NMOS電晶體以改善感測速度。 此外，使用電荷再利用的技巧以減少多級感測放大器的功率消耗。 其與傳統的多級放大器比較之下，其改善了6.1ns (24%) 的感測速度和節省了25.6% 的功率。 第二，一個改善的靜態功率降低 (SPR) 電路被描述。 我們提出的靜態電流截止靜態功率降低 (SCCSPR) 電路使用了電容升壓的技巧，它關閉了SPR電路中永遠導通的MOS電晶體，因此我們設計的電路與傳統SPR電路比較之下，其功率消耗減少了30.9%。 第三，一個改善的電壓倍增電路被發展。 在我們提出的電路中使用了間接開關，其提供較大的閘源極偏壓給PMOS 傳輸電晶體，因此電流驅動能力與升壓速度都被改善了。 在供應電壓2V時，我們改良的電壓倍增電路與傳統的比較之下，其升壓速度大約提升18.6%。

此篇論文中的三個高性能電路被應用在1-Kbit 動態隨機存取記憶體當中。 當供應電壓在2V時，我們可以得到36ns 的存取時間以及52.58mW的總功率消耗。 其與傳統動態隨機存取記憶體相較之下，減少了10.3ns (22.2%) 的存取時間與6.44mW (11%) 的功率消耗。

Three high performance circuits for a low power supply DRAM’s are presented in this thesis. First, a modified multi-stage sense amplifier is proposed, that utilizes the auxiliary transmission gate and charge recycling technique. The auxiliary NMOS transistor of the multi-stage sense amplifier is replaced by the transmission gate to improve the sensing speed. In addition, the charge recycling technique is used to reduce the power dissipation of multi-stage sense amplifier. It improves the sensing time by 6.1ns (24.4%) compared to that of the conventional multi-stage sense amplifier and the power saving percentage of 25.6% compared to that of the conventional one. Second, an improved Standby Power Reduction (SPR) Circuit is reported. The capacitor boosting technique is utilized in our proposed Static Current Cut-off Standby Power Reduction (SCCSPR) Circuit, which turns off the always-on MOS transistor of SPR circuit. The power consumption is 30.9% reduced by our design compared to that of the conventional SPR circuit. Third, an improved voltage doubler is developed. The indirect switch is utilized in our proposed circuit, it provides larger gate source bias applied to the PMOS pass transistor. Thus, the current drivability is arisen and the pumping speed is improved as well. In the 2V supply voltage, the pumping speed of our modified voltage doubler is arisen about 18.6% compared to that of the conventional voltage doubler.
These high performance circuits in this thesis are applied in a 1-Kbit DRAM circuits. A data access time of 36ns and total power consumption 52.58mW are attained when the supply voltage is 2V. The access time of 10.3ns (22.2%) and power consumption of 6.44mW (11%) are reduced compared to that of the conventional DRAM.

Contents
Chapter 1 Introduction.............................................................…….1

Chapter 2 Basic Architecture of DRAM...............…………........3
2.1 Storage Element………………………………………………….3
2.2 Address Decoder.............................…...........................................3
2.3 Sense Amplifier..............................…...........................................7
2.4 Voltage Generator..........................…..........................................10

Chapter 3 Modified Multi-Stage Sense Amplifier……...........15
3.1 Conventional Multi-Stage Sense Amplifier………….................15
3.2 N&PMOS Cross-Coupled Sense Amplifier…............................18
3.3 Improved N&PMOS Cross-Coupled Sense Amplifier…............24
3.4 Simulation Result……………………….....................................27

Chapter 4 The Peripheral Circuits of DRAM….......................33
4.1 The Peripheral Circuits for Reducing Standby Power....…..…...33
4.2 Modified Peripheral Circuit for Reducing Standby Power..…....36
4.3 Modified Voltage Doubler…………………………………...…44

Chapter 5 Simulation Results of the DRAM Using High Performance Circuits Proposed……..........................……..........53

Chapter 6 Conclusion..............................................………….........62

Reference.....................................................................…………..........64

Appendix.....................................................................…………..........67

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