本論文前半段推導了一時變除頻值鎖相迴路模型，利用此模型探討傳統分數式、應用差異積分調制器之頻率合成器的理論。並且利用上述之模型推導及模擬閉迴路調制架構對調制訊號資料傳輸率的限制;最後擴及推導與模擬雙點閉迴路調制式架構。後半段，則利用FPGA設計分數式頻率合成器加上高斯頻率鍵移調制電路與補償雙點差異積分調制路徑間增益與延遲不匹配電路後，完成一2.4GHz跳頻方式之展頻發射機，可完全滿足藍芽系統之規格要求。

In the first, a time-variant modulus phase lock loop(PLL) model is established. Applying the model, Theorems of fractional-N synthesizers are introduced. We also explain theorems and simulations of Closed-Loop Modulation and Two-Point Delta Sigma Modulation with the model. In the end, a 2.4GHz FHSS transmitter using Two-Point Delta Sigma Modulation which meets Bluetooth specifications is demonstrated.

目錄
目錄I
圖表目錄 II
第一章 前言1
第二章 分數式頻率合成器之理論與模擬4
2.1 數位與類比訊號轉換4
2.2 整數除頻式頻率合成器之雜訊形成與抑制9
2.3 傳統分數式頻率合成器18
2.4 差異積分調變器雜訊抑制法21
第三章 雙點差異積分調制架構理論與模擬30
3.1 傳統閉迴路調制式頻率合成器30
3.2 利用電壓控制振盪器進行調制之系統響應 34
3.3 雙點差異積分調制式頻率合成器36
第四章跳頻方式展頻系統發射機之設計與實做40
4.1差異積分調製器之電路設計與實作40
4.2跳頻通道選擇數列之設計與實作43
4.3分數式頻率合成器之設計與實作44
4.4數位高斯濾波器之設計與實作46
4.5數位類比轉換器模組製作47
4.6 雙點電壓控制振盪器製作 47
4.7發射機跳頻與調制性能測試50
第五章結論58
參考文獻59

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