由於傳統的陰極射線管顯示器(CRT)已經被液晶平面顯示器所替代，隨著平面顯示器的尺寸增大，身為開關元件的非晶矽薄膜電晶體的性能、品質上的要求也越來越高。
在本論文中，我們改良了傳統的雙閘極電晶體構造，製造出利用銦錫氧化物(ITO)做為背閘極的非對稱雙閘極電晶體結構。我們定義做為背閘極的ITO電極只覆蓋於汲極端的上方，且由汲極端覆蓋到傳導通道的一半。這個新式元件保留了雙閘極電晶體的優點，其元件的性能各方面都比傳統的電晶體優越。不僅擁有較高的導通電流，而且在照光下也具有較低的光漏電流。
另外，我們利用非對稱雙閘極電晶體的結構來探討寄生電容的問題。藉由C-V量測方法去驗證這個新結構也降低了雙閘極電晶體的回踢電壓過大的問題。除此之外，由於結構的非對稱性，我們也探討了源極與汲極互換後會對元件的電性造成不同的影響。最後，我們利用stress模式去探討元件的可靠度機制。可以得知，這個新式元件的劣化速度在長時間操作下會和傳統結構差不多。

The traditional displayer – CRT has already been substituted by liquid crystal displayer (LCD).The a-Si TFT is used to be a switch, while the size of the displayer increases, the require of the performance and quality of TFTs is more and more better. Therefore, it is very important subject to study the stability and to improve the performance of a-Si TFTs.
In this thesis, we fabricate another new structure (asymmetry dual-gate TFTs).For asymmetry dual-gate TFTs, the ITO back gate is extended to the middle of the channel and only covered on the drain contact. The new structure has the advantages of dual-gate TFTs. With dual-channel conduction, it exhibit higher Ion and lower photo leakage current performance than the conventional inverted staggered TFTs.
In addition, we use the asymmetry dual-gate structure to investigate how the parasitic capacitance influences the feed-through voltage by C-V measurement. We also to investigate the influences of electrical characteristics with the ITO back gate whether or not overlap the source contact. The asymmetry in on current with source-drain swapping can be attributed to the difference in the ITO back gate whether overlaps the source contact. Finally, it simulated the process of the degradation on the TFTs to find the stability mechanism of the TFTs.

Contents

ABSTRACT(CHINESE) I
ABSTRACT II
ACKNOWLEDGEMENT(CHINESE) III
CONTENTS IV
FIGURE CAPTIONS VI
CHAPTER 1 INTRODUCTION 1
CHAPTER 2 BACKGROUND OF A-SI:H TFTS 4
2.1 HYDROGENATED AMORPHOUS SILICON 4
2.2 ATOMIC STRUCTURE AND THE ELECTRON DENSITY OF STATES 4
2.3 PHOTO LEAKAGE CURRENT MECHANISM 7
2.4 CAPACITANCE-VOLTAGE CHARACTERISTICS OF A-SI:H TFTS 10
2.5 BIAS INDUCED METASTABILITY 11
2.5.1 Charge trapping 11
2.5.2 Defect state creation 12
CHAPTER 3 FABRICATION AND CHARACTERIZATION 14
3.1 DEVICE STRUCTURE AND FABRICATION 14
3.2 APPARATUS 15
3.3 SET UP INSTRUMENTS FOR I-V AND C-V MEASUREMENT 16
3.4 METHOD OF DEVICE PARAMETER EXTRACTION 17
3.4.1 Determination of the threshold voltage 17
3.4.2 Determination of the subthreshold swing 17
3.4.3 Determination of the field-effect mobility 18
3.4.4 Determination of on/off current ratio 18
CHAPTER 4 RESULTS AND DISCUSSIONS 20
4.1 DUAL-GATE A-SI:H TFTS ELECTRICAL PERFORMANCE 20
4.1.1 I-V characteristics 20
4.1.2 C-V characteristics 21
4.2 ASYMMETRY DUAL-GATE A-SI:H TFTS ELECTRICAL PERFORMANCE 23
4.2.1 C-V characteristics 23
4.2.2 I-V characteristics 24
4.2.3 Forward mode and reverse mode 25
4.3 THE RELIABILITY OF DC STRESS 26
CHAPTER 5 CONCLUSIONS 27
REFERENCE 28
FIGURES 31

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