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博碩士論文 etd-0709113-092337 詳細資訊
Title page for etd-0709113-092337
論文名稱
Title
新穎高集積密度省電之非傳統互補式穿隧式場效電晶體反相器的探討
Study of Novel High Integration-Density and Low Power Non-classical CTFET Inverter
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
165
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2013-07-18
繳交日期
Date of Submission
2013-08-09
關鍵字
Keywords
互補式穿隧場效電晶體反相器、低功率、閘極控制、穿隧式場效電晶體、高集積密度、矽覆絕緣
Gated control, SOI (Silicon on Insulator), TFET, Low power, High packing density, CTFET
統計
Statistics
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The thesis/dissertation has been browsed 5742 times, has been downloaded 1364 times.
中文摘要
本研究主要探討由負型穿隧場效電晶體當作驅動電晶體,並以閘極控制I-I-P電晶體當作負載電晶體之新穎互補式穿隧場效電晶體反相器及其特性與分析。我們命名此新穎互補式穿隧場效電晶體反相器為“CGTFET”。根據第四章的結果,本研究所提出之新穎互補式穿隧場效電晶體反相器有正確的邏輯特性,延遲時間較傳統互補式穿隧場效電晶體反相器(CTFET)雖然較慢,但是卻大幅改良了互補式穿隧場效電晶體反相器的電壓過衝現象,並且保持其功率消耗極小於傳統互補式金氧半反相器(CMOS)。此外,由於驅動器與負載器兩元件為矽覆絕緣(SOI),而且結構之間的摻雜區域可共享形成共享輸出節點,兩元件之間無須物理性隔離結構,可以大幅提升集積密度。佈局面積較傳統互補式金氧半反相器(Bulk-CMOS)減少至39.2 %,較矽覆絕緣互補式金氧半反相器(SOI-CMOS)減少至45.3 %,較矽覆絕緣互補式穿隧場效電晶體反相器(SOI-CTFET)減少至65.4 %,更重要的是降低製程步驟。因此,我們相信,本研究所提出之具高集積密度、製程步驟簡易之新穎互補式穿隧場效電晶體反相器可以成為未來下世代互補式穿隧場效電晶體反相器的最佳候選之一。
Abstract
The research discusses a novel CTFET inverter which is composed of a N-typed TFET(NTFET) as a driven transistor and a Gated control I-I-P transistor as a loaded transistor, and discusses its characteristic and analysis. We name it “CGTFET”. According to the results, our proposed CGTFET inverter has correct logic behavior and its delay time is little slow when compared with the conventional CTFET. However, the CGTFET improves voltage overshoot phenomenon of the CTFET, and the power consumption of the CGTFET is lower than the conventional CMOS. In addition, because of the SOI structure and the N-type shared output node, our proposed CGTFET does not need any physical isolation technique, thereby improving the packing density. Our proposed CGTFET indeed obtain a 39.2 % reduction of the total area compared with the conventional Bulk-CMOS. Our proposed CGTFET also can achieve a 45.3 % reduction in the total area when compared with the SOI-CMOS. Our proposed CGTFET indeed obtain a 65.4 % reduction of the total area compared with the SOI-CTFET. More importantly, due to the reduced process steps, the cost reduction can be achieved. We therefore believe that a high packing density novel CTFET inverter with reduced process steps can become one of the contenders for future CTFET scaling.
目次 Table of Contents
第一章-緒論 1
1.1背景 1
1.1.1改變材料 4
1.1.2使用應力技術 14
1.1.3改變結構 18
1.2動機 22
第二章-物理機制與元件操作原理 24
2.1物理機制 24
2.1.1穿隧場效電晶體 (TFET) 物理與操作機制 24
2.1.1.a能帶至能帶穿隧傳輸 (Band-to-band tunneling transmission) 26
2.1.1.b能隙窄化機制 (Bandgap narrowing mechanism) 28
2.1.1.c與濃度相關的產生復合 ( The doping dependence of the SRH Generation-Recombination )[37-38] 29
2.1.2閘極控制IIP電晶體 29
2.2新穎邏輯元件操作理論與原理 39
2.2.1.傳統互補式金氧半邏輯閘操作理論與原理 39
2.2.2.傳統互補式穿隧式場效電晶體邏輯閘操作理論與原理 46
2.2.3.以負型穿隧場效電晶體及閘極控制I-I-P電晶體所構成之新穎具共享摻雜區域互補式穿隧場效電晶體反相器 51
第三章-元件架構設計與製程 56
3.1元件架構設計 56
3.1.1以負型穿隧場效電晶體及閘極控制I-I-P電晶體所構成之新穎具共享摻雜區域互補式穿隧場效電晶體反相器 56
3.1.2以鍺源極之負型穿隧場效電晶體及閘極控制I-I-P電晶體所構成之新穎具共享摻雜區域互補式穿隧場效電晶體反相器 65
3.1.3以閘極控制N-I-I電晶體及正型穿隧場效電晶體所構成之新穎具共享摻雜區域互補式穿隧場效電晶體反相器 69
第四章-模擬結果與討論 72
4.1元件模擬之物理模型 72
4.2電性分析與討論 75
4.2.1以負型穿隧場效電晶體及閘極控制I-I-P電晶體所構成之新穎具共享摻雜區域互補式穿隧場效電晶體反相器電性分析 75
4.2.2以鍺源極負型穿隧場效電晶體及閘極控制I-I-P電晶體所構成之新穎具共享摻雜區域互補式穿隧場效電晶體反相器電性分析 83
4.2.3新穎具共享摻雜區域互補式穿隧場效電晶體反相器的最佳化 89
4.2.4電性比較和佈局圖比較 99
第五章-實作結果和檢討 102
第六章-結論與未來展望 128
6.1結論 128
6.2未來展望 129
參考文獻 130
附錄 139
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