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論文名稱 Title |
三個改良的具低功率低電壓之運算放大器 Three improved operational amplifiers with low power low voltage |
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系所名稱 Department |
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畢業學年期 Year, semester |
語文別 Language |
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學位類別 Degree |
頁數 Number of pages |
52 |
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研究生 Author |
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指導教授 Advisor |
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召集委員 Convenor |
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口試委員 Advisory Committee |
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口試日期 Date of Exam |
2001-06-28 |
繳交日期 Date of Submission |
2001-07-10 |
關鍵字 Keywords |
運算放大器、低功率低電壓 low power low voltage, CMOS operational amplifier, rail-to-rail |
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統計 Statistics |
本論文已被瀏覽 5721 次,被下載 5050 次 The thesis/dissertation has been browsed 5721 times, has been downloaded 5050 times. |
中文摘要 |
提出三種改良的具有低電壓與端對端固定轉導之運算放大器。之中的兩個放大器改良了具有準位偏移電路之運算放大器。一個改良了使其具有較少之元件數,較快之速度並減少了所佔用之面積。而另一個改良的放大器則是加上了可調增益之功能。第三個改良了浮動電壓控制電壓源之運算放大器,使其所佔用之面積減少並且亦改良了其頻率響應。 首兩個準位偏移運算放大器以聯電0.5μm CMOS製程來設計。它們只使用了約為原始電路的一半之元件數來完成功能。供應電壓為1.3 V,而電流損耗約為原始電路的22.6%。單增益頻率增加了56.8%。Slew rate,CMRR與PSRR亦比原來之電路還要高。第二個電路仍具有端對端固定轉導之功能;然而,其轉導是可以調整的。第三個電路使用聯電0.35μm CMOS製程技術具有1.2V的操作電壓。增益頻寬積比原來之電路高53.8%。無須任何之頻率補償電路而具有較少之面積。以上所有之結果皆以HSPICE模擬完成。 |
Abstract |
Three improved operational amplifiers with low voltage and rail-to-rail constant are proposed. Two of the amplifiers are modified from the amplifier with a level shifting circuit. One improved amplifier has fewer devices, higher speed, and reduced area and the other improved amplifier is added an additional adjustable gain. The third amplifier is a floating voltage controlled voltage source (FVCVS) amplifier, which has reduced area and improved frequency response. The first two level shifting operational amplifiers are designed in a 0.5μm UMC CMOS process. They use about half number of devices. The supply voltage is 1.3V, and the current consumes just only 22.6% of the original circuits. The unity gain frequency increases 56.8%. The slew rate, CMRR and PSRR are higher. The 2nd amplifier still has a rail-to-rail constant gm; however, the gm can be adjusted. The third amplifier uses the 0.35μm UMC CMOS process with 1.2V operating voltage. The gain-bandwidth product is 53.8% larger than the original circuits. No frequency compensation is used and the devices are fewer. The results are obtained in HSPICE simulation. |
目次 Table of Contents |
Contents Ⅰ. Introduction Ⅰ-1~Ⅰ-4 Ⅱ. The rail-to-rail CMOS operational amplifier with level shifting Ⅱ-1 1. The circuits Ⅱ-1 1.1 Principle of level shifting Ⅱ-1~Ⅱ-2 1.2 The circuit designed by J. Francisco Duque-carillo Ⅱ-3~Ⅱ-5 2. Level shifting with constant rail-to-rail transconductance Ⅱ-6~Ⅱ-7 Ⅲ. The novel level shifting circuit for the rail-to-rail CMOS operational amplifier Ⅲ-1 1. The proposed level-shifting circuit Ⅲ-1~Ⅲ-3 2. Simulation results Ⅲ-4~Ⅲ-9 Ⅳ. The novel low voltage adjustable gain amplifier Ⅳ-1 1. Variations of the bias currents of the complementary input stage with level shift Ⅳ-1~Ⅳ-2 2. The proposed op amp with adjustable gm Ⅳ-3~Ⅳ-7 3. Simulation results Ⅳ-8~Ⅳ-10 Ⅴ. The floating voltage controlled voltage source amplifier Ⅴ-1 1. The FVCVS operational amplifier Ⅴ-1 2. The implementation of the FVCVS operational amplifier Ⅴ-2~Ⅴ-3 Ⅵ. The improved FVCVS operational amplifier Ⅵ-1 1. The proposed operational amplifier Ⅵ-1~Ⅵ-2 2. Simulation results Ⅵ-3~Ⅵ-4 Ⅶ. Conclusion Ⅶ-1 |
參考文獻 References |
[1] Coban, A.L.; Allen, P.E.; Xudong Shi, “Low-voltage analog IC design in CMOS technology”, IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Vol. 42, Issue: 11, pp 955-958, Nov. 1995. [2] R.Jacob Baker, CMOS circuit design, layout, and simulation, New York, pp 608-611, 1998. [3] William Redman-White, “A High Bandwidth Constant gm and Slew-Rate Rail-to-Rail CMOS Input Circuit and its Application to Analog Cells for Low Voltage VLSI Systems”, IEEE Journal of Solid-State Circuits, Vol. 32, No. 5, May 1997. [4] C. Hwang, A. Motamed, and M. Ismail, “Universal constant-gm input-stage architectures for low-voltage op amps ”, Circuits and Systems I: Fundamental Theory and Applications, IEEE Transactions on, Vol. 42, no.11, pp 886-895, Nov. 1995. [5] J. Francisco Duque-Carrillo, José L. Ausín, Guido Torelli, José M. Valverde, Miguel A. Domínguez, “1-V rail-to-rail operational amplifiers in standard CMOS technology”, IEEE Journal of Solid-State Circuits.Vol.35, no.1, pp 33-44, January 2000. [6] Minsheng Wang, Terry L. Mayhugh, Jr., Sherif H.K. Embabi, and Edgar Sánchez-Sinencio, “Constant-gm rail-to-rail CMOS Op-Amp input stage with overlapped transition regions”, IEEE Journal of Solid-State Circuits.Vol.34, no.2, pp 148-156, February 1999. [7] J. Ramírez-Angulo, A. Torralba, R. G. Carvajal, and J. Tombs, “Low-Voltage CMOS Operational Amplifiers with Wide Input–Output Swing Based on a Novel Scheme”, IEEE Transactions on Circuits and Systems-I: fundamental theory and application, vol. 47, no. 5, May 2000. |
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