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博碩士論文 etd-0710106-193304 詳細資訊
Title page for etd-0710106-193304
論文名稱
Title
雙臨界電壓邏輯單元之低功率前看進位加法器與適用於DVB-T 之低成本數位I/Q分離器
A Low-power High-speed 8-bit Pipelining CLA Design Using Dual Threshold Voltage Domino Logic and Low-cost Digital I/Q Separator for DVB-T
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
58
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2006-06-20
繳交日期
Date of Submission
2006-07-10
關鍵字
Keywords
數位I/Q分離器、雙臨界電壓骨牌式邏輯電路、前看進位加法器
Dual Threshold Voltage Domino Logic, Carry Look-ahead Adder, Digital I/Q Separator
統計
Statistics
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中文摘要
本論文包含兩個主題,第一個主題是介紹一使用雙臨界電壓邏輯單元之低功率前看進位加法器。第二個題目為介紹一適用於DVB-T 之低成本數位I/Q 分離器。
使用雙臨界電壓邏輯單元之低功率前看進位加法器,該雙臨界電壓邏輯單元,依據電路之充電路徑(precharge phase)和計算路徑(evaluation phase)特性不同,在充電路徑上使用高臨界電壓電晶體,減少漏電流的產生,降低功率消耗;在計算路徑上使用低臨界電壓電晶體,縮短延遲,加快速度。又特別在該骨牌式邏輯單元的輸出級反相器多加一個由時脈控制的N 型電晶體,使其可適用於高速的管線式架構又可效節省功率消耗。因此,由該雙臨界電壓邏輯單元組成之前看進位加法器在保有高速運算的優點下,又同時擁有低功率的特點。
適用於DVB-T 之低成本數位I/Q 分離器,使用數位方式實踐傳統類比式I/Q 分離器,有效地克服了由於類比元件特性所造成的增益(gain mismatch)、相位差(phase mismatch)不平衡現象。又透過適當演算法簡化,可將原本需要兩個類比數位轉換器、兩個混波器、兩個低通濾波器的高成本類比I/Q 分離器,替換成只需使用ㄧ個類比數位轉換器、多個反相器和移位器所組成的數位I/Q 分離器,達到低成本的優點。
Abstract
This thesis includes two topics. One is a low-power high-speed 8-bit pipelining CLA design using dual threshold voltage (dual- Vth) domino logic. The other is a low-cost digital I/Q separator for DVB-T receivers.
A high speed and low power 8-bit CLA using dual- Vth domino logic blocks arranged in a PLA-like style with pipelining is presented. According to parallely precharge and sequentially evaluate in a cascaded set of domino logic blocks, transistors in the precharge part and the evaluation part of dual- Vth domino logic are, respectively, replaced by high Vth transistors to reduce subthreshold leakage current through OFF transistors, and low Vth transistors. Moreover, an nMOS transistor is inserted in the precharge phase of the output inverter such that the two-phase dual- Vth domino logic can be properly applied in a pipeline structure. Consequently, the proposed design keeps the advantage of high speed while attaining the effect of low power dissipation.
A low-cost digital I/Q separator is presented in the second part of this thesis. Using digital I/Q separator in place of the traditional analog I/Q separator guarantees the design conquer gain and phase mismatch problems between the I and Q channels. The proposed design can berealized by inverters and shifters such that the goal of low cost can be achieved.
目次 Table of Contents
摘要............................................................................................................. i
Abstract ...................................................................................................... ii
第一章 簡介...........................................................................................1
1.1 加法器相關研究與研究動機.....................................................1
1.2 I/Q 分離器相關研究與研究動機...............................................3
1.3 論文目的.....................................................................................5
1.4 論文大綱.....................................................................................5
第二章 雙臨界電壓邏輯單元之低功率前看進位加法器...................7
2.1 概論.............................................................................................7
2.2 原理概述.....................................................................................8
2.3 架構與原理說明.........................................................................9
2.3.1 雙臨界電壓邏輯單元.......................................................9
2.3.2 前看進位加法器設計.....................................................14
2.3.3 可程式化邏輯陣列之管線式電路設計.........................15
2.4 分析...........................................................................................18
2.4.1 速度分析.........................................................................18
2.4.2 面積分析.........................................................................19
2.5 電路的模擬與量測...................................................................22
2.5.1 佈局後模擬波型與結果.................................................22
2.5.2 晶片量測結果與波形圖.................................................24
2.5.3 晶片佈局圖和照像圖.....................................................27
2.5.4 晶片量測結果討論.........................................................28
第三章 適用於DVB-T 之低成本數位I/Q 分離器.............................29
3.1 概論...........................................................................................29
3.2 I/Q 分離原理.............................................................................30
3.3 I/Q 分離器實作.........................................................................32
3.3.1 類比作法分析.................................................................32
3.3.2 數位作法分析.................................................................33
3.3.3 數位I/Q 分離器實現......................................................36
3.3.4 模擬與結果.....................................................................39
3.4 I/Q 分離器佈局圖與預計規格.................................................41
第四章 結論.............................................................................................43
參考文獻...................................................................................................45
參考文獻 References
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