本論文提出彎曲平板波(Flexural-Plate-Wave, FPW)過敏原感測系統所需之分貝線性可程式化可變增益放大器，以及具數位校正之電壓峰值偵測器。
第一個主題探討一分貝線性可程式化可變增益放大器。本設計以源極追隨器做為輸入端，可接收極低直流準位之輸入訊號。並將輸入電壓與輸出電流呈線性關係的局部迴授(local-feedback)轉導電路，設計為轉導級與負載級。只要利用數位控制開關改變轉導級與負載級之轉導值大小，即可改變本設計之增益。除此之外，本設計亦利用一重配置方法，藉由數位輸入訊號之MSB使轉導級與負載級交換，可減少佈局面積並改善增益變動的線性度，可達到小於0.86 dB的增益誤差。
第二個主題為探討一具數位校正之電壓峰值偵測器。本設計的電壓峰值偵測方法為，利用積分器、數位類比轉換器與電壓比較器，產生一負緣落在輸入弦波訊號波峰處的方波訊號，利用此方波訊號觸發取樣及維持電路即可偵測電壓峰值。而數位校正方法是藉由狀態訊號產生器所輸出的兩狀態訊號，分別取樣及維持對應至不同數位類比轉換器電壓值的兩電壓峰值。再將此兩電壓峰值輸入一電壓比較器，校正控制器讀取電壓比較器之輸出，以得出能偵測到最小電壓誤差的數位類比轉換器輸出電壓值。藉由所提出的數位校正方法，可偵測頻率20 MHz弦波的電壓峰值，而所偵測到的電壓峰值誤差小於0.81 %。

This thesis proposes a dB-linear programmable variable gain amplifier (VGA) and a voltage peak detector with digital calibration for FPW-based antibody sensing system.
In the first topic, a dB-linear programmable variable gain amplifier is proposed. By using two source followers as the input terminals, input signals with very low DC offset could be received. The linear local-feedback transconductors are employed to be trans-condurctor-stage and load-stage. Besides, a reconfiguration method is used to reduce the layout area and improve the linearity of the gain to attain gain error less than 0.86 dB measured on silicon.
In the second topic, a voltage peak detector with digital calibration is proposed. The voltage peak of the input sine-wave signal is sampled and held by using an integra-tor, a digital-to-analog converter, and a voltage comparator to generate a square-wave signal. Besides, the voltage error caused by the propagation delay could be calibrated by the proposed digital calibration method. The frequency of input signal is up to 20 MHz and the voltage error is justified to be less than 0.81 % by simulations.

致謝 i
摘要 ii
Abstract iii
目錄 iv
圖目錄 vi
表目錄 ix
第一章 概論 1
1.1 研究動機 1
1.2 相關技術與文獻探討 2
1.2.1 FPW過敏原感測系統 2
1.2.2 可程式化可變增益放大器 3
1.2.3 電壓峰值偵測器 4
1.3 論文大綱 6
第二章 分貝線性可程式化可變增益放大器 8
2.1 簡介 8
2.2 可變增益放大器整體架構 8
2.3 可變增益放大器電路設計 10
2.3.1 源極追隨器級 10
2.3.2 重配置可變增益級分析 11
2.3.3 局部迴授轉導電路分析 15
2.3.4 重配置編碼器 17
2.3.5 電壓除法器 18
2.3.6 共模迴授電路 20
2.3.7 偏壓電路 20
2.4 可變增益放大器電路模擬與佈局 21
2.4.1 電路佈局後模擬結果 21
2.4.2 電路佈局 24
2.4.3 預計規格 26
2.5 可變增益放大器晶片實作與量測 27
2.5.1 晶片照相圖 27
2.5.2 晶片量測結果 28
2.5.3 效能比較 30
2.6 結果與討論 31
第三章 具數位校正之電壓峰值偵測器 33
3.1 簡介 33
3.2 電壓峰值偵測器整體架構 33
3.3 電壓峰值偵測器電路設計 35
3.3.1 積分器 35
3.3.2 數位類比轉換器 36
3.3.3 狀態訊號產生器 37
3.3.4 校正控制器 38
3.4 電壓峰值偵測器電路模擬與佈局 40
3.4.1 電路佈局後模擬結果 40
3.4.2 電路佈局 43
3.4.3 預計規格與效能比較 45
3.5 電壓峰值偵測器晶片實作與量測 46
3.6 結果與討論 51
第四章 結論與未來研究方向 53
參考文獻 56

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