本論文包含兩主題：兩倍供應電壓輸出緩衝器電壓迴轉率補償之製程與溫度偵測器，以及具製程、電壓及溫度補償與自我調節電壓迴轉率控制器之兩倍供應電壓輸出緩衝器。
第一個主題探討一個兩倍供應電壓輸出緩衝器電壓迴轉率補償之製程與溫度偵測器。對於偵測電路部分，本設計分別利用N型電晶體與P型電晶體之門檻電壓分別偵測N型電晶體與P型電晶體所落在製程的角落。兩倍供應電壓輸出級的驅動電流在不同的製程與溫度環境下會不同，例如在較差的角落下，兩倍供應電壓輸出級的驅動電流會較低，此時偵測電路會補償兩倍供應電壓輸出級的驅動電流；而在較佳的角落下，兩倍供應電壓輸出級的驅動電流會較高，此時偵測電路會降低兩倍供應電壓輸出級的驅動電流，使兩倍供應電壓輸出級之電壓迴轉率在不同的製程與溫度環境下的變異縮小。
第二個主題探討一具製程、電壓及溫度補償與自我調節電壓迴轉率控制器之兩倍供應電壓輸出緩衝器。其對於製程偵測電路部分，與第一個主題相同，是分別利用N型與P型電晶體之門檻電壓偵測N型與P型電晶體所落在的角落，並補償。而電壓及溫度偵測電路部分，則是利用PMOS電晶體之基體效應來偵測與補償。進而使輸出級之電壓迴轉率在不同的製程、電壓與溫度環境下的變異縮小。

This thesis is composed of two designs: a PT (process, temperature) detector for 2×VDD output buffer with slew rate compensation, and a slew rate self-adjusting 2×VDD output buffer with PVT compensation.
In the first topic, a PT detector for 2×VDD output buffer with slew-rate compensa-tion is proposed. The driving current of 2×VDD output stages varies provided that the process and temperature conditions are different. For example, the driving current of 2×VDD output stage will be low at poor PVT corners. By contrast, the driving current will be high at good PVT corners. The process corner and temperature of NMOS and PMOS should be detected by threshold voltage variation thereof, respectively, such that the slew rate compensation is feasible. The proposed sensors will carry out the PT de-tection and compensate the driving current based on the detected corner, such that the slew rate variation of the output stage will be reduced.
The second topic is a slew rate self-adjusting 2×VDD output buffer with PVT compensation. An NMOS and PMOS process detector is proposed to detect the process corners of NMOS and PMOS, respectively, while the voltage and temperature sensor is proposed to detect the voltage and temperature variations by body effect.

致謝 i
摘要 ii
Abstract iii
目錄 iv
圖次 vi
表次 ix
第一章 概論 1
1.1 研究動機 1
1.2 相關技術與文獻探討 4
1.2.1 傳統輸出輸入單元 4
1.2.2 先前文獻中之混合電壓共容輸出入緩衝器 5
1.2.3 先前文獻中之製程、電壓與溫度變異偵測電路 5
1.3 論文大綱 7
第二章 兩倍供應電壓輸出緩衝器電壓迴轉率補償之製程與溫度偵測器 9
2.1 簡介 9
2.2 PT偵測器電路架構 9
2.3 PT偵測器電路設計 10
2.3.1 製程與溫度偵測器 10
2.3.2 製程與溫度判斷器 15
2.3.3 兩倍供應電壓輸出緩衝器 17
2.4 PT偵測器電路模擬 23
2.4.1 電壓迴轉率補償結果 23
2.4.2 預計規格 24
2.5 晶片佈局 24
2.6 晶片實測與量測結果 26
2.7 結果與討論 30
第三章 具製程、電壓及溫度補償與自我調節電壓迴轉率控制器之兩倍供應電壓輸出緩衝器 31
3.1 簡介 31
3.2 PVT偵測器電路架構 31
3.3 電路設計 32
3.3.1 PVT偵測器 (PVT sensor) 32
3.3.2 PVT判斷器 (PVT decider) 36
3.3.3 輸出緩衝器 (Output buffer) 37
3.4 PVT偵測器電路模擬 40
3.4.1 電壓迴轉率補償結果 40
3.4.2 預計規格 41
3.5 晶片佈局 42
3.6 晶片實作與量測結果 43
3.7 結果與討論 47
第四章 研究結果與結論 48
參考文獻 51
附錄A 54
附錄B 56

[1] International Technology Roadmap for Semiconductors（ITRS）, Semiconductor Industry Association, 2002.
[2] 劉人瑋, “3倍VDD之雙向混合電壓共容輸入輸出緩衝器與具有製程及溫度補償之2倍VDD輸出緩衝器,” 國立中山大學電機工程學系碩士班碩士論文, 2010.
[3] B. Razavi, “Short-channel effects and device models,” in Design of Analog CMOS Integrated Circuits, 1st ed., New York: Mcgraw-Hill, 2001, pp. 599-600.
[4] F. Klass, A. Jain, and G. Hess, “An on-chip process control monitor for process variability measurements in nanometer technologies,” in Proc. IEEE Int. Conf. IC Design and Technology, pp. 203-206, Jul. 2009
[5] T. Iizuka, J. Jeong, T. Nakura, M. Ikeda, and K. Asada, “All-digital on-chip monitor for PMOS and NMOS process variability measurement utilizing buffer ring with pulse counter,” in Proc. IEEE European Solid-State Circuits Conf., pp. 182-185, Nov. 2010.
[6] R.-C. Kuo, H.-Y. Tseng, J.-W. Liu, and C.-C. Wang, “On-Chip process and tem-perature compensation and self-adjusting slew rate control for output buffer,” IEEE Asia Pacific Conf. on Postgraduate Research Microelectronics and Elec-tronics, pp. 37-41, Oct. 2011.
[7] K. Leung, “Controlled slew rate output buffer,” in Proc. IEEE Custom Integrat-ed Circuits Conf., pp. 5.5/1-5.5/4, May 1988.
[8] S.-K. Shin, W. Yu, Y.-H. Jun, J.-W. Kim, B.-S. Kong, and C.-G. Lee, “A slew rate controlled output driver using PLL as compensation circuit,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1227-1233, Jul. 2003.
[9] 侯筱涵, “具高可靠度之新式混合電壓共容輸出輸入緩衝器設計,” 國立中山大學電機工程學系碩士班碩士論文, 2011.
[10] J. Williams, “Mixing 3 V and 5 V ICs,” IEEE Spectrum, vol. 30, no. 3, pp. 40-42, Mar. 1993.
[11] T. Furukawa, D. Turner, S. Mittl, M. Maloney, R. Serafin, W. Clark, J. Bialas, L. Longenbach, and J. Howard, “Accelerated gate-oxide breakdown in mixed- voltage I/O circuits,” in Proc. IEEE Int. Reliability Physics Symp., pp. 169-173, Apr. 1997.
[12] E. Takeda and N. Suzuki, “An empirical model for device degradation due to hot-carrier injection,” IEEE Electron Device Letter, vol. 4, no. 4, pp. 111-113, Apr. 1983.
[13] M.-D. Ker, S.-L. Chen, and C.-S. Tsai, “Overview and design of mixed-voltage I/O buffers with low-voltage thin-oxide CMOS transistors,” IEEE Trans. Circuit and Systems I: Regular Papers, vol. 53, no. 9, pp. 1934-1945, Sep. 2006.
[14] M. J. M. Pelgrom and E. C. Dijkmans, “A 3/5 V compatible I/O buffer,” IEEE J. Solid-State Circuits, vol. 30, no. 7, pp. 823-825, Jul. 1995.
[15] M.-D. Ker and C.-S. Tsai, “Design of 2.5 V/5 V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic n-well bias circuit,” in Proc. IEEE Int. Symp. on Circuits and Systems, vol. 5, pp. V-97-V-100, May 2003.
[16] C.-H. Chung and M.-D. Ker, “Design on mixed-voltage-tolerant I/O interface with novel tracking circuit in a 0.13-μm CMOS technology,” in Proc. IEEE Int. Symp. on Circuits and Systems, vol. 2, pp. 577-580, May 2004.
[17] Y.-H. Kwak, I. Jung, H.-D. Lee, Y.-J. Choi, Y. Kumar, and C. Kim, “A one cy-cle lock time slew-rate-controlled output driver,” IEEE Int. Solid-State Circuits Conf. Dig. Tech. Papers, pp. 408-611, Feb. 2007.
[18] M.-D. Ker, T.-M. Wang, and F.-L. Hu, “Design on mixed-voltage I/O buffers with slew-rate control in low-voltage CMOS process,” in Proc. 15th IEEE Int. Conf. on Electronic, Circuits and Systems, pp. 1047-1050, Nov. 2008.
[19] V. Narang, B. Arya, and K. Rajagopal, “Novel low delay slew rate control I/Os,” in Proc. 1st Asia Symp. on Quality Electronic Design, pp. 189-193, Aug. 2009.
[20] T. Matano, Y. Takai, T. Takahashi, Y. Sakito, I. Fujii, Y. Takaishi, H. Fujisawa, S. Kubouchi, S. Narui, K. Arai, M. Morino, M. Nakamura, S. Miyatake, T. Sekiguchi, and K. Koyama, “A 1-Gb/s/pin 512-Mb DDRII SDRAM using a dig-ital DLL and a slew-rate-controlled output buffer,” IEEE J. Solid-State Circuits, vol. 38, no. 5, pp. 762-768, May 2003.
[21] S.-K. Shin, W. Yu, Y.-H. Jun, J.-W. Kim, B.-S. Kong, and C.-G. Lee, “A slew rate controlled output driver using PLL as compensation circuit,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1227-1233, Jul. 2003.
[22] Q. A. Khan, G. K. Siddhartha, D. Tripathi, S. K. Wadhwa, and K. Misri, “Tech-niques for on-chip process voltage and temperature detection and compensa-tion,” in Proc. Int. Conf. on VLSI Design, pp. 1-6, Jan. 2006.
[23] R. J. Baker, CMOS circuit design, layout, and simulation, 3rd ed., New Jersey: John Wiley & Sons, 2010, pp. 135-140, pp. 293-296.
[24] C.-L. Chen, H.-Y. Tseng, R.-C. Kuo, and C.-C. Wang, “A slew rate self-adjusting 2×VDD output buffer with PVT compensation,” in Proc. IEEE Int. Symp. on VLSI Design, Automation and Test, (accepted, paper no. M14, Apr. 2012)
[25] A. Sanyal, A. Rastogi, W. Chen, and S. Kundu, “An efficient technique for leakage current estimation in nanoscaled CMOS circuits incorporating self-loading effects,” IEEE Trans. Computers, vol. 59, no. 7, pp. 922-932, Jul. 2010.