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博碩士論文 etd-0710115-105801 詳細資訊
Title page for etd-0710115-105801
論文名稱
Title
多重精確度貼圖單元的設計與實作
Design and Implementation of a Multi-precision Texture Unit
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
64
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2015-07-27
繳交日期
Date of Submission
2015-08-10
關鍵字
Keywords
像素著色器、三維圖形處理器、多重精確度設計、低功率設計、貼圖單元
Pixel Shader, 3-D Graphics Processing Unit, Multi-precision Design, Low-power Design, Texture Unit
統計
Statistics
本論文已被瀏覽 5656 次,被下載 51
The thesis/dissertation has been browsed 5656 times, has been downloaded 51 times.
中文摘要
近年來隨著三維繪圖處理器的進步,使用者對於圖像的要求也越來越高,除了成像要美觀且精準之外,對於效能及功率消耗亦有所要求。而貼圖單元在三維繪圖處理器當中便佔了一個非常重要的角色,貼圖單元不但可以增加成像的細膩程度,達到擬真的效果外,更可以藉由貼圖行為取代並減少部分的計算。換句話說,在三維繪圖處理器中使用貼圖單元,不僅可以使圖像更精美,許多繁複的運算還可以直接使用貼圖單元來進行,使整體三維繪圖處理器效能更好,產生的圖片品質更高。但因人眼在先天視覺上便有其限制,對於三維影像的輕微失真並無法準確分辨,故本論文提出一個多重精確度貼圖單元的架構,其目的是在可以允許失真的情況下,提供多重精確度供使用者選擇,若是重視輸出品質則可選擇最高精準度,假如較低品質也可以接受時,則可藉由犧牲些許精準度,來降低功率消耗。
Abstract
With the rapid development of 3-D graphics processing units (3-D GPUs), users ask more high quality, more high performance, and more low power consumption for 3-D graphics applications. As a result, texture unit is becoming more important in 3-D GPUs. Texture unit is able to rotate and resize a bitmap to be placed onto an arbitrary plane of a given 3D object as a texture, leading to more details and high quality for the images. In this thesis, texture unit is implemented as a separate processor to deal with the texture operations and enhance the performance of 3-D GPUs. Besides, human eyes can’t recognize a slight distortion of 3-D images. Therefore, minimizing the precision of texture operations under the acceptable accuracy loss can reduce the power consumption of texture unit. Accordingly, we propose the hardware architecture of a multi-precision texture unit, which can change the computation precisions for trading the power efficiency with the quality of the rendered image. Lower precision can be selected to significantly reduce the power consumption of texture unit when the accuracy loss is allowable.
目次 Table of Contents
論文審定書 i
論文提要 ii
誌謝 iii
摘要 iv
Abstract v
目錄 vi
圖目錄 viii
表目錄 x
第一章 緒論 1
1.1 研究動機 1
1.2 論文大綱 2
第二章 研究背景 3
2.1 三維繪圖概述 3
2.2 ATTILA模擬器 5
2.2.1 模擬器架構 5
2.2.2 驗證流程 10
2.3 貼圖單元 11
2.3.1 Texture mapping 11
2.3.2 Texture filter 15
第三章 多重精確度之貼圖單元 18
3.1 貼圖單元之資料流程介紹 18
3.2 貼圖單元之基本架構 19
3.2.1 Calculate Address 21
3.2.2 Fetch and Read 24
3.2.3 Filter 25
3.2.4 Controller 31
第四章 研究方法與成果 34
4.1 實驗步驟與方法 34
4.2 實驗結果 37
第五章 結論與未來研究方向 50
5.1 結論 50
5.2 未來研究方向 50
參考文獻 52
參考文獻 References
[1] 李鈺珊,“應用於三維繪圖處理器之低功率指令模式調整系統”, 國立中山大學資訊工程學系碩士論文, July 2014.
[2] Chung-Ping Chung, Hong-Wei Chen, Hui-Chin Yang, “Designed and Implemented of Graphics Rasterization Algorithm with FPGA,” IET International Communication Conference on Wireless Mobile and Computing, pp. 325-328, November 2011.
[3] Chung-Ping Chung, Hong-Wei Chen, Hui-Chin Yang, “Blocked-Z Test for Reducing Rasterization, Z Test and Shading Workloads,” IEEE International Conference on Computational Science and Engineering, pp. 402-407, 2009.
[4] Woo-Chan Park, Il-San Kim, Tack-Don Han, Sung-Bong Yang, “An Effective Pixel Rasterization Pipeline Architecture for 3D Rendering Processors,” IEEE Transactions on Computers, pp. 1501-1508, November 2003.
[5] ATTILA: http://attila.ac.upc.edu/wiki/index.php/Main_Page
[6] Victor Moya del Barrio, Carlos González, Jordi Roca, Agustín Fernández, and Roger Espasa, “ATTILA: A Cycle-Level Execution-Driven Simulator for Modern GPU Architectures,” IEEE International Symposium on Performance Analysis of Systems and Software, pp. 231-241, March 2006.
[7] ARB Vertex Program Extension:
http://oss.sgi.com/projects/ogl-sample/registry/ARB/vertex_program.txt
[8] ARB Fragment Program Extension:
http://oss.sgi.com/projects/ogl-sample/registry/ARB/fragment_program.txt
[9] Hengyong Jiangl, Xuzhi Wang, Mengyao Zhu, Wanggen Wan, Yanru Ma, “A Novel Triangle Rasterization Algorithm Based on Edge Function,” IEEE Cross Strait Quad-Regional Radio Science and Wireless Technology Conference, pp. 1235-1238, July 2011
[10] Woo-Chan Park, Kil-Whan Lee, Il-San Kim, Tack-Don Han, and Sung-Bong Yang, “A Mid-texturing Pixel Rasterization Pipeline Architecture for 3D Rendering Processors,” IEEE International Conference on Application-Specific Systems, Architectures, and Processors, 2002
[11] Ramchan Woo, Sungdae Choi, Ju-Ho Sohn, Seong-Jun Song, Young-Don Bae, and Hoi-Jun Yoo, “A Low-Power 3-D Rendering Engine With Two Texture Units and 29-Mb Embedded DRAM for 3G Multimedia Terminals,” IEEE Journal of Solid-state Circuits, pp. 1101-1109, July 2004
[12] Jeong-Ho Woo, Min-Wuk Lee, Hyejung Kim, Ju-Ho Sohn and Hoi-Jun Yoo, “A 1.2Mpixels/s/mW 3-D Rendering Processor For Portable Multimedia Application,” IEEE Asian Solid-State Circuits Conference, pp. 297-300, November 2005
[13] Victor Moya del Barrio, Carlos González, Jordi Roca, Agustín Fernández, and Roger Espasa, “ATTILA: A Cycle-Level Execution-Driven Simulator for Modern GPU Architectures,” IEEE International Symposium on Performance Analysis of Systems and Software, pp. 231-241, March 2006
[14] 劉哲宇,“基於砌塊式繪圖架構之三維繪圖著色引擎的設計、分析與實現”, 國立成功大學電腦與通信工程研究所碩士論文, July 2009
[15] Nearest filter示意圖:
http://www.neogaf.com/forum/showthread.php?t=817792&page=26
[16] Yusra A. Y. Al-Najjar, and Dr. Der Chen Soong, “Comparison of Image Quality Assessment: PSNR, HVS, SSIM, UIQI,” International Journal of Scientific & Engineering Research, Vol. 3, No. 8, August 2012.
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