隨著科技的日新月異與三維繪圖處理器技術的成熟，三維繪圖處理器已經被廣泛的應用在穿戴式裝置，而穿戴式裝置對於繪圖處理器的繪圖能力需求也越來越高。但這些複雜的運算將消耗大量電力，因此如何在電池容量有限的穿戴式裝置節省功率的消耗就成為一個重要的議題。在三維繪圖處理器中，貼圖單元扮演一個不可或缺的角色。貼圖單元可以讓影像看起來更加細緻，並且可以利用貼圖來代替複雜的計算，以提升整體處理器的效能與影像的畫質。人類的眼睛可以允許影像有些許失真而無法察覺差異，所以我們引進多重精確度的概念，在允許影像有些許失真的情況下，執行我們選定的精確度模式，達到節省功率的效果。另外，我們可以觀察到貼圖單元需要進行很多複雜的運算，而這些運算可以利用多個內積運算指令(DP4)來完成，因此我們設計一個供貼圖單元使用的內積運算單元(DP4)，並且透過貼圖單元的管線化架構來增加效能。　
　　本論文提出一個多重精確度貼圖單元的管線化架構，此架構可以提供多種精確度模式給使用者選擇，達到降低功率消耗的目標。此外，我們也在貼圖單元中加入快取機制以增加效能，並且重複執行內積運算單元來實現線性過濾功能，用以降低硬體的面積。最後我們將貼圖單元的運算進行管線化排程，並且設計對應的管線化架構，大大地提升貼圖單元的整體效能。

As technology advances and the fully developed technology for 3-D graphics processing units, it has been widely applied in wearable devices. For wearable devices, the performance requirement of graphics processor unit performance is increasing, Unfortunately, these complex operations will consume a lot of power. Therefore, how to reduce the power consumption within the limited power of wearable devices has become an important issue. The texture unit is an indispensable part in the 3-D graphics processing units. The texture unit can make the image more details and high quality. In addition, it can use texture mapping to substitute complex computations, so that the overall performance and image quality of 3-D graphics processing units can be enhanced. Human eyes can’t clearly recognize a slight distortion of 3-D images. As a result, power savings can be achieved by selecting lower precisions mode when a little image distortion is acceptable. Besides, there is many complex computations in texture unit. These computations can be implemented by several dot product (DP4) instructions. Therefore, we design a dot product unit for texture unit to enhance the performance by a pipelined architecture.
This thesis proposes a pipelined architecture for multi-precision texture unit. The architecture can change the computation precision to save power consumption. In addition, we add cache mechanism in texture unit to increase performance, and the dot product arithmetic unit is executed repeatedly to implement linear filter. As a result, the area of hardware circuit can be decreased. Finally, we perform pipelined scheduling for texture unit, and design the corresponding pipelined architecture that greatly enhances overall performance.

論文提要 i
摘要 ii
Abstract iii
目錄 v
圖目錄 vii
表目錄 x
第一章 緒論 1
1.1 研究動機 1
1.2 論文大綱 2
第二章 研究背景 3
2.1 三維繪圖介紹 3
2.2 OPENGL ES簡介 6
2.3 ATTILA 3D繪圖模擬器 8
2.4 運算單元 11
2.4.1 布斯編碼器 11
2.4.2 壓縮樹 15
2.4.3 布斯乘法器 17
2.5 貼圖單元 18
2.5.1 Texture mapping 18
2.5.2 Mipmap 19
2.5.3 Texture Filter 21
第三章 多重精確度貼圖單元之管線化架構 24
3.1 貼圖單元流程介紹 24
3.2 基礎貼圖單元架構 25
3.2.1 Calculate Address 27
3.2.2 Fetch and Read 28
3.2.3 Filter 29
3.3 提出的貼圖單元架構 33
3.3.1 快取機制 35
3.3.2 內積運算單元 36
3.3.3 Multi-precision 39
3.3.4 管線化排程 40
3.3.5 Controller 42
第四章 實驗方法與成果 43
4.1 實驗步驟與方法 43
4.2 實驗結果 46
第五章 結論與未來研究方向 58
5.1 結論 58
5.2 未來研究方向 58
參考文獻 59

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