摘要
二維材料因低維度所致的獨特性質，不僅在基礎物理研究上提供良好的平台，也為科技發展中所遭遇的瓶頸，例如：再續摩爾定律（Moore’s Law），提供可能的解決之道。近來，越來越多以二維材料設計的元件擁有超越傳統半導體元件的效能。日前，我們發現III-VI族硒化銦（InSe），從可見光到近紅外光波段具有很好的光響應（photoresponsivity） (~ 12.3 A/W)。而本論文旨在進一步研究硒化銦背向式閘極場效電晶體(back-gate field-effect transistor)的基本電性與遲滯現象(Hysteresis)的成因並評估作為記憶體的可能性。透過量測ID-VG轉換特性曲線圖，發現硒化銦為N型半導體，載子遷移率(Mobility)為0.75 (cm2/Vs)，具有高開關電流比值與遲滯現象的發生。藉由ID-T載子保留時間曲線圖(retention time)，發現不同通道厚度(5 nm, 6 nm與11 nm)元件皆具有載子被表面缺陷(surface defects)長時間捕獲之記憶體特性，時間分別為2315天、300天與234天，並且以通道厚度(5 nm)之結果最為顯著，原因為表面缺陷/載子濃度(carrier concentration)之比值較高。此外，透過氧電漿處理能進一步製造更多缺陷延長載子保留時間，並由通道電流對應時間圖(ID-T)確定載子保留時間分別為9250天、4600天與1850天。通道表面缺陷可以由X射線光電子能譜(X-ray photoelectron spectroscopy, XPS)確定為氧化銦(In2O3)；想要了解元件是否具有反覆儲存電荷(set)與移除電荷(reset)特性，我們透過施加正負交錯脈衝閘極電壓實驗可以顯示元件記憶體具有反覆儲存能力。最後由以上結果確認本研究之元件是透過表面缺陷來儲存電荷達到非揮發性記憶體特性，不需要像傳統式快閃記憶體必須額外透過電荷儲存層來儲存電荷，其優點還包含製程步驟簡化以及可以達到元件垂方向的尺寸微縮。

關鍵字：二維材料、硒化銦、硒化銦電晶體、遲滯現象、缺陷、記憶體。

Abstract
Two-dimensional materials serve not only as good platforms for exploration of condensed matter physics, but also alternative materials to keep up with Moore’s Law due to their low dimensional characteristics. Recently, our group have found that the indium selenide (InSe) belonged to III-VI groups has high photo-responsivity (~ 12.3 A/W) in wavelengths from visible to infrared light. Based on these results, we take one step further to investigate the fundamental electrical properties and hysteresis phenomenon of the back-gate field-effect transistors to be possible applications for memory devices. InSe exhibits N-type semiconductor characteristic, high switching current ratio, and the carrier mobility is 0.75 (cm2/Vs) based on the ID-VG measurements. Interestingly, our devices show hysteresis phenomenon and long retention time. Such phenomenon is because that carriers are captured by surface defects. Furthermore, we find the InSe devices with different channel thickness (5 nm, 6 nm and 11 nm) all have long retention time (2315 days, 300 days, and 234 days, respectively). We conclude the reason is because of the highest the ratio of the surface defects and carrier concentration. Moreover, retention time of devices with different thickness (5 nm, 6 nm and 11 nm) can be further extended (9250 days, 4600 days, and 1850 days, respectively) after oxygen plasma treatments. We further determined the structure of the defects is indium oxide (In2O3) through X-ray photoelectron spectroscopy (XPS).
To sum up, we demonstrated that InSe field-effect transistors have potential applications in memory devices. Unlike the traditional flash memory devices which need a storage layer to store charge, this proposed device has advantage of simplified process steps and vertical scaling down.




Keywords：Two-dimensional materials, Indium Selenium, InSe-FET, Hysteresis, defects, memory.

目錄
論文審定書 i
誌謝 ii
摘要 iii
Abstract iv
目錄 vi
圖目錄 viii
表目錄 xi
第一章.序論 1
1.1前言 1
1.2快閃記憶體 4
1.3研究動機 6
1.4二維材料應用於記憶體之文獻回顧 10
1.4.1石墨烯鐵電記憶體 11
1.4.2石墨烯快閃記憶體及二硫化鉬快閃記憶體 13
1.4.3二維材料電阻式記憶體 16
1.4.4二維材料可撓式記憶體 20
1.4.5二維材料應用於光電記憶體 21
1.5 硒化銦(InSe)材料特性 22
第二章.參數定義解釋與儀器介紹 24
2.1參數定義解釋 24
2.1.1電流與載子遷移率 25
2.1.2臨界電壓 26
2.1.3載子滯留持續時間 26
2.1.4缺陷捕獲電荷數量 26
2.2儀器介紹 27
第三章.元件製程步驟與結構 32
3.1元件製程步驟 32
3.1.1 矽/二氧化矽(Si/SiO2)基板清洗 32
3.1.2硒化銦(InSe)轉黏至基板與電極定義區域 33
3.1.3雙電子槍蒸鍍機蒸鍍電極與兩吋石英管狀化學氣相沉積系統退火 37
3.1.4感應耦合式電漿蝕刻系統之氧電漿態過程 38
3.2元件結構 39
第四章.實驗結果與討論 41
4.1元件基本電性量測 41
4.2不同通道厚度元件之遲滯特性 46
4.3硒化銦(InSe)記憶體之物理機制 50
4.4不同通道厚度元件透過感應耦合式電漿蝕刻系統(ICP-Etcher)氧電漿(O2 plasma)處理之記憶體特性 52
4.5最適當通道厚度之記憶體特性分析 58
第五章.結論 62
參考文獻 63

參考文獻
[1] Hardee, Kim C., David B. Chapman, and Juan Pineda. “Dynamic random access memory.” United States Patent No. 5,077,693, 1991.
[2] Cho, W. J., & Choi, K. J. “Static random access memory.” United States Patent No. 5,381,046, 1995.
[3] Meena, J. S., Sze, S. M., Chand, U., & Tseng, T. Y. “Overview of emerging nonvolatile memory technologies.” Nanoscale research letters. 9, 1-33, 2014.
[4] Zhang, Guobiao. “Three-dimensional read-only memory.” United States Patent No. 5,835,396, 1998.
[5] Aritome, Seiichi. “Advanced flash memory technology and trends for file storage application.” Electron Devices Meeting. Technical Digest. Institute of Electrical and Electronics Engineers. 763-766, 2000.
[6] Bez, R., Camerlenghi, E., Modelli, A., & Visconti, A. “Introduction to flash memory.” Institute of Electrical and Electronics Engineers. 91, 489-502, 2003.
[7] Masuoka, F., Momodomi, M., Iwata, Y., & Shirota, R. “New ultra high density EPROM and flash EEPROM with NAND structure cell.” Electron Devices Meeting, International. Institute of Electrical and Electronics Engineers. 33, 552-555, 1987.
[8] Pavan, P., Bez, R., Olivo, P., & Zanoni, E. “Flash memory cells-an overview.” Institute of Electrical and Electronics Engineers. 85, 1248-1271, 1997.
[9] Kahng, Dawon, and Simon M. Sze. “A floating gate and its application to memory devices.” Bell System Technical Journal. 46, 1288-1295, 1967.
[10] White, M. H., Yang, Y., Purwar, A., & French, M. L. “A low voltage SONOS nonvolatile semiconductor memory technology.” Components, Packaging, and Manufacturing Technology, Part A, Institute of Electrical and Electronics Engineers. 20, 190-195, 1997.
[11] Bez, R., Camerlenghi, E., Modelli, A., & Visconti, A. “Introduction to flash memory.” Institute of Electrical and Electronics Engineers. 91, 489-502, 2003
[12] Momodomi, M., Masuoka, F., Shirota, R., Itoh, Y., Ohuchi, K., & Kirisawa, R. “Electrically erasable programmable read-only memory with NAND cell structure.” United States Patent No. 4,959,812, 1990.
[13] Tickle, Andrew C. “Electrically erasable programmable read-only memory.” United States Patent No. 4,377,857, 1983.
[14] “International Technology Roadmap for Semiconductors” update from 2011 International Technology Roadmap for Semiconductors reports.
[15] “Global Semiconductor Devices：Application, Market, and Trend Analysis.” Topology Research Institute, Taipei, Taiwan, 2010.
[16] “The Intel processors will be the future 3D transistors” update from Intel 22 nm Technology.
[17] Troutman, R. R. “VLSI limitations from drain-induced barrier lowering.” IEEE Journal of Solid-State Circuits. 14, 383-391, 1979.
[18] Sarkar, D., Xie, X., Liu, W., Cao, W., Kang, J., Gong, Y., & Banerjee, K. “A subthermionic tunnel field-effect transistor with an atomically thin channel.” Nature. 526, 91-95, 2015.
[19] Sarkar, D., Liu, W., Xie, X., Anselmo, A. C., Mitragotri, S., & Banerjee, K. “MoS2 field-effect transistor for next-generation label-free biosensors.” American Chemical Society Nano. 8, 3992-4003, 2014
[20] Cao, W., Kang, J., Sarkar, D., Liu, W. & Banerjee, K. “Performance evaluation and design considerations of 2D semiconductor based FETs for sub-10 nm VLSI.” In IEEE International Electron Devices Meeting. 30, 1-4, 2014.
[21] Frank, D. J., Dennard, R. H., Nowak, E., Solomon, P. M., Taur, Y., & Wong, H. S. P. “Device scaling limits of Si MOSFETs and their application dependencies. ” Proceedings of the IEEE. 89, 259-288, 2001.
[22] Novoselov, K. S., Geim, A. K., Morozov, S. V., Jiang, D., Zhang, Y., Dubonos, S. V., & Firsov, A. A. “Electric field effect in atomically thin carbon films.” Science. 306, 666-669, 2004.
[23] Radisavljevic, B., Radenovic, A., Brivio, J., Giacometti, I. V., & Kis, A. “Single-layer MoS2 transistors.” Nature nanotechnology. 6, 147-150, 2011.
[24] Lopez-Sanchez, O., Lembke, D., Kayci, M., Radenovic, A., & Kis, A. “Ultrasensitive photodetectors based on monolayer MoS2.” Nature nanotechnology. 8, 497-501, 2013.
[25] Tsai, M. L., Su, S. H., Chang, J. K., Tsai, D. S., Chen, C. H., Wu, C. I., ... & He, J. H. “ Monolayer MoS2 heterojunction solar cells.” American Chemical Society Nano. 8, 8317-8322, 2014.
[26]Zheng, Y., Ni, G. X., Toh, C. T., Zeng, M. G., Chen, S. T., Yao, K., & Özyilmaz, B. “Gate-controlled nonvolatile graphene-ferroelectric memory.” Applied Physics Letters. 94, 163505, 2009.
[27] Song, E. B., Lian, B., Kim, S. M., Lee, S., Chung, T. K., Wang, M., & Rasool, H. I. “Robust bi-stable memory operation in single-layer graphene ferroelectric memory.” Applied Physics Letters. 99, 042109, 2011.
[28] Wang, X., Xie, W., & Xu, J. B. “Graphene Based Non-Volatile Memory Devices.” Advanced Materials. 26, 5496-5503, 2014.
[29] Hong, A. J., Song, E. B., Yu, H. S., Allen, M. J., Kim, J., Fowler, J. D., ... & Kaner, R. B. “Graphene flash memory.” American Chemical Society Nano. 5, 7812-7817, 2011.
[30] Lee, S. Y., Duong, D. L., Vu, Q. A., Jin, Y., Kim, P., & Lee, Y. H. “Chemically modulated band gap in bilayer graphene memory transistors with high on/off ratio.” American Chemical Society Nano. 9, 9034-9042, 2015.
[31] Bertolazzi, Simone, Daria Krasnozhon, and Andras Kis. “Nonvolatile memory cells based on MoS2/graphene heterostructures.” American Chemical Society Nano. 7, 3246-3252, 2013.
[32] Zhang, E., Wang, W., Zhang, C., Jin, Y., Zhu, G., Sun, Q., & Xiu, F. “Tunable charge-trap memory based on few-layer MoS2.” American Chemical Society Nano. 9, 612-619, 2014
[33] Waser, Rainer, and Masakazu Aono. “Nanoionics-based resistive switching memories.” Nature materials. 6, 833-840, 2007.
[34] Sawa, A. “Resistive Switching in Transition Metal Oxides.” Mater. Today. 11, 28-36, 2008.
[35] Mikolajick, T. Salinga, M. Kund, M. Kever, T. “Nonvolatile Memory Concepts Based on Resistive Switching in Inorganic Materials.” Advanced Engineering Materials. 11, 235-240, 2009.
[36] Waser, R.; Dittmann, R.; Staikov, G.; Szot, K. “Redox-Based Resistive Switching Memories - Nanoionic Mechanisms, Prospects, and Challenges.” Advanced Engineering Materials. 21, 2632-2663, 2009.
[37] Beck, A.; Bednorz, J. G.; Gerber, C.; Rossel, C.; Widmer, D. “Reproducible Switching Effect in Thin Oxide Films for Memory Applications.” Applied Physics Letters. 77, 139-141, 2000.
[38] Yang, Y. C.; Chen, C.; Zeng, F.; Pan, F. “Multilevel Resistance Switching in Cu/TaOx/Pt Structures Induced by a Coupled Mechanism.” Journal of Applied Physics. 107, 093701-1–093701-5, 2010.
[39] Yu, S. M.; Wu, Y.; Wong, H. S. P. “Investigating the Switching Dynamics and Multilevel Capability of Bipolar Metal Oxide Resistive Switching Memory.” Applied Physics Letters. 98, 103514-1–103514-3, 2011.
[40] He, C., Shi, Z., Zhang, L., Yang, W., Yang, R., Shi, D., & Zhang, G. “Multilevel resistive switching in planar graphene/SiO2 nanogap structures.” American Chemical Society Nano. 6, 4214-4221, 2012.
[41] Wang, X., Xie, W., Du, J., Wang, C., Zhao, N., & Xu, J. B. “Graphene/metal contacts: bistable states and novel memory devices.” Advanced Materials. 24, 2614-2619, 2012.
[42] Xu, X. Y., Yin, Z. Y., Xu, C. X., Dai, J., & Hu, J. G. “Resistive switching memories in MoS2 nanosphere assemblies.” Applied Physics Letters, 104, 033504, 2014.
[43] Zhuang, X. D., Chen, Y., Liu, G., Li, P. P., Zhu, C. X., Kang, E. T., ... & Li, Y. X. “Conjugated‐Polymer‐Functionalized Graphene Oxide: Synthesis and Nonvolatile Rewritable Memory Effect.” Advanced materials, 22, 1731-1735, 2010.
[44] Byrd, Terry Anthony, and Douglas E. Turner. “An exploratory examination of the relationship between flexible IT infrastructure and competitive advantage.” Information & Management. 39, 41-52, 2001.
[45] Son, D. I., Kim, T. W., Shim, J. H., Jung, J. H., Lee, D. U., Lee, J. M., ... & Choi, W. K. “Flexible organic bistable devices based on graphene embedded in an insulating poly (methyl methacrylate) polymer layer.” Nano letters, 10, 2441-2447, 2010.
[46] Lei, S., Wen, F., Li, B., Wang, Q., Huang, Y., Gong, Y., & Ge, L. “Optoelectronic memory using two-dimensional materials.” Nano letters. 15, 259-265, 2014.
[47] L. Debbichi., O. Eriksson., & S. Lebègue. “Two-Dimensional Indium Selenides Compounds: An Ab Initio Study.” American Chemical Society Letters. 6, 3098-3103, 2015.
[48] landaY. Depeursinge, E. Doni., R. Girlanda., A. Baldereschi., & K. Maschke. “Electronic properties of the layer semiconductor.” Solid State Communications. 27, 1449-1453, 1978.
[49] “雙電子槍蒸鍍機(Dual E-Beam Evaporator)” 下載於科技部高屏地區奈米核心設施共同實驗室之雙電子槍蒸鍍機操作手冊。
[50] “感應耦合式電漿蝕刻系統(Inductive Couple Plasma Etcher)” 下載於科技部高屏地區奈米核心設施共同實驗室之感應耦合式電漿蝕刻系統操作手冊。
[51] Balitskii, O. A., Savchyn, V. P., & Yukhymchuk, V. O. “Raman investigation of InSe and GaSe single-crystals oxidation.” Semiconductor science and technology. 17, L1, 2002.
[52] Elouali, S., Bloor, L. G., Binions, R., Parkin, I. P., Carmalt, C. J., & Darr, J. A. “Gas sensing with nano-indium oxides (In2O3) prepared via continuous hydrothermal flow synthesis.” Langmuir, 28, 1879-1885, 2012.