在高速數位電路中，多個高速緩衝器同步切換時所需之暫態電流會在積體電路、封裝及印刷電路板產生顯著的接地彈跳雜訊(GBN)。GBN會造成一些訊號完整性的問題，例如短時脈衝波干擾(glitches)、時序上的誤差(timing push-out)及電磁干擾(EMI)等問題。隨著時脈訊號速度增加及系統中電源電壓變低，GBN成為影響數位電路特性的主要因素之ㄧ。
在電源及接地面間加去耦合電容以抑制GBN為一般常見的作法，但一般來講由於引腳的電感性使電容在高頻處失去抑制效果。最近有人提出新的抑制GBN的方法，即在電源或接地面上設計電磁能隙結構。目前已發表出幾種不同的電磁能隙結構錸增加抑制GBN的頻寬，但皆有一些缺點。例如高阻抗表面結構(HIS)需要三到四層金屬層才能做到，所以製作成本較高，若要達到寬頻的效果則需要串接多個不同頻段的結構，在設計上需較大空間。
本論文中提出一種新的電磁能隙結構來達到寬頻的效果。此新結構在數學上及實驗上皆已證明對GBN有10GHz的抑制效果。最後我們提出合併高低介電係數材料與EBG結構去控制禁止帶的位置及頻寬。

Transient current surges resulted from the simultaneous switching of output buffers in the high-speed digital circuits can induce significant ground bounce noise (GBN) on the chip, package, and printed circuit board (PCB). The GBN not only causes the signal integrity (SI) problems, such as glitches or timing push-out of signal traces, but also increases the electromagnetic interference (EMI) in the high-speed digital circuits. With the design trends of digital circuits toward higher speed, low voltage level, smaller volume, the impact of GBN has become one of the most important issues that determine the performance of electronic products.
Adding decoupling capacitors between the power and ground planes is a typical way to suppress the GBN. However, they are not effective at the frequencies higher than 600MHz due to their inherent lead inductance. Recently, a new idea for eliminating the GBN is proposed by designing electromagnetic bandgap (EBG) structure with high impedance surface (HIS) on the ground or power plane. Several new EBG power/ground plane designs have been proposed to broaden the stopband bandwidth for suppressing the GBN. However there are some drawbacks, such as high cost, large area occupation and complicated fabrication process.
In this paper, we propose a novel Hybrid EBG power planes for PCB or package to suppress the GBN. Its extinctive behavior of broadband suppression of GBN (over 10GHz) is demonstrated experientially and numerically. Finally, we combine the periodic high-low dielectric material with the EBG power plane to control the position and bandwidth of stopband.

第一章 序論 01
1.1 研究背景與動機 01
1.2 論文大綱 03
第二章常見抑制接地彈跳雜訊的對策 04
2.1切割電源平面對接地彈跳雜訊的抑制效果 04
2.1.1 切割電源平面對電源品質的影響 04
2.1.2 切割電源平面對電磁干擾影響 07
2.2 去耦合電容對電磁干擾影響 08
2.3 Low-period coplanar electromagnetic bandgap (LPC-EBG) structure
對接地彈跳雜訊的抑制效果 10
2.3.1 LPC-EBG對電源品質的影響 10
2.4 High impedance surface對接地彈跳雜訊的抑制效果 13
2.5 Fork-like EBG 結構對接地彈跳雜訊的抑制效果 14
第三章 L-bridged EBG 結構探討 17
3.1 L-bridged EBG 結構之設計概念 17
3.2 L-bridge EBG 結構對接地彈跳抑制雜訊的效果 18
3.3 L-bridged EBG結構的禁止帶模型(stopband model) 21
3.3.1 頻率與傳播常數關係式推導 21
3.3.2 Lump model中電感電容值的估計 23
3.4 L-bridge EBG結構對訊號完整性的影響 26
3.5 L-bridge EBG結構對電磁干擾(EMI)的影響 28
第四章 Hybrid EBG結構探討 31
4.1 Hybrid EBG 結構設計及PCB板接地彈跳抑制效果 31
4.2 Hybrid EBG 結構在封裝架構下對接地彈跳抑制效果 33
4.2.1 Hybrid EBG結構的禁止帶模型(stopband model) 38
4.2.2 Lump model中電感電容值的估計 41
第五章利用高低介電係數材料以增加禁止帶頻寬 44
5.1 2D-FDTD計算EBG結構的頻帶結構(band structure)及 44
模態能量場形分佈
5.2高低介電係數材料應用概念之模擬驗證 46
第六章 結論 49
附錄A 50
A.1 FDTD 演算法 50
A.1.1馬克斯威爾方程式 50
A1.2三維方程式 50
A.1.3中央差分與Yee網格配置 51
A.1.4邊界條件 53
A.2二維方程式 54
A.2.1 TMz模態之中央差分與網格配置 55
A.2.2 TMz模態之邊界條件 56
A.2.3 網格大小與穩定準則 56
A.2.4 阻抗性電壓源 57
A.3 一維方式之微帶線 57
A.3.1 電報方程式 57
A.3.2 輸入端與輸出端 59
A.3.3 電報方程式與2D FDTD結合 61
A.3.4 微帶線 62
A.3.5 槽孔與電源供應平面 62
參考文獻 67

[1] J.G.Yook, V. Chandramouli,L.P.B. Katehi, K. A. Sakallah, T. R. Arabi, and T. A. Schreyer, “Computation of switching noise in printed circuit board”, IEEE Trans. Comp., Packag., and Manufact., vol. 20, pp. 64-75, Mar. 1997.
[2] G. T. Lei, R. W. Techentin, and B. K. Gilbert, “High-frequency characterization of power/ground-plane structures”,IEEE Trans. Microwave Theory Tech., vol. 47, pp.562-569, May. 1999.
[3] 黃峻南，“多層高速數位電路板中接地彈跳效應對電源品質及電磁輻射干擾之模擬及量測”，中山大學碩士論文第三章，3-1~3.7,June 2002.
[4] T. L. Wu, S. T. Chen, J. N. Huang and Y. H. Lin, “Numerical and experimental investigation of radiation caused by the switching noise on the partitioned DC reference planes of high speed digital PCB,” IEEE Trans. on Electromagnetic Compatibility, vol. 46, pp. 33-45, Feb. 2004.
[5] Gisin, F.; Pantic-Tanner, Z., “Edge emissions from a PC board structure, ” in
Proc. of IEEE Int. Symp. on EMC, 2001, pp. 1333-1334.
[6] O. M. Ramahi, “Near-field and Far-field calculation in FDTD simulations using Kirchhoff surface integral representation,” IEEE Trans. on Antennas Propagat., vol. 45, pp. 753-759, May 1997.
[7] Y. H. Lin and T. L. Wu, “Investigation of signal quality and radiated emission of microstrip line on imperfect ground plane: FDTD analysis and measurement,” in Proc IEEE Int. Symp. Electromagnetic Compatibility, vol.1, 2001, pp. 319-324.
[8] T. L. Wu, Y. H. Lin and S. T. Chen, “A Novel Power Planes With Low Radiation and Broadband Suppression of Ground Bounce Noise Using Photonic Bandgap Structures,” IEEE Microwave and Wireless Components Letters, vol. 14, pp. 337-339, July 2004.
[9] R. Coccioli, F. R. Yang, K. P. Ma and T. Itoh, “Aperture-coupled patch antenna on UC-PBG substrate,” IEEE Trans. Microwave Theory & Tech., vol. 47, pp. 2123-2130, Nov. 1999.
[10] N. Shino and Z. Popovic´, “Radiation from ground-plane photonic bandgap microstrip waveguide,” IEEE MTT-S Int. Microwave Symp. Dig., June 2002, pp. 1079–1082.
[11] R. Abhari, and G. V. Eleftheriades, “Metallo-dielectric electromagnetic bandgap structures for suppression and isolation of the parallel-plate noise in high-speed circuits,” IEEE Trans. Microwave Theory & Tech., vol. 51, pp. 1629-1639, June 2003.
[12] T. Kamgaing, and O. M. Ramahi, “A novel power plane with integrated simultaneous switching noise mitigation capability using high impedance surface,” IEEE Microwave and Wireless Components Letters, vol. 13, pp. 21-23, January 2003.
[13] D. F. Sievenpiper, “High-impedance electromagnetic surfaces,”Ph.D. dissertation, Dept. Elect. Eng., Univ. California at Los Angeles, Los Angeles, CA, 1999.
[14] Li Yang, Mingyan Fan, Fanglu Chen, Jingzhao She, and Zhenghe Feng“A novel compact electromagnetic-bandgap (EBG) structure and its applications for microwave circuits”IEEE Trans. Microwave Theory and Techniques, vol. 53, pp. 183 - 190, Jan. 2005.
[15] Li Yang, Zhenghe Feng, Fanglu Chen, and Mingyan Fan“A novel compact electromagnetic band-gap (EBG) structure and its application in microstrip antenna arrays” IEEE MTT-S Int. Microwave Symp. Dig. pp.1635 – 1638, vol 3, June 2004.
[16] S. Van den Berghe, F. Olyslager, D. De Zutter, J. De Moerloose, and W. Temmerman, “Study of the ground bounce caused by power plane resonances,” IEEE Trans. Electromagn. Compat., vol. 40, May 1998, pp.111-119.
[17] J. Chen, T. H. Hubing, T. P. Van Doren, and R. E. DuBroff, “Power bus isolation using power islands in printed circuit boards,” IEEE Trans. Electromag. Compat., vol. 44, May 2002, pp. 373 -380.
[18] W. Cui, J. Fan, H. Shi, and J. L. Drewniak, “DC power bus noise isolation with power islands,” IEEE Int. Symp. Electromag. Compat., 2001, pp.899-903.
[19] C. R. Paul, “Incorporation of terminal constraints in the FDTD analysis of transmission lines,” IEEE Trans. Electromag. Compat., vol. 36, May 1994, pp. 85-91.
[20] T. P. Montoya, “Modeling 1-D FDTD transmission line voltage sources and terminations with parallel and series RLC loads,” IEEE Int. Symp. Anten. and Propa. Soc., vol. 4, 2002, pp.242-245.
[21] C. T. Wu, G. H. Shiue, S. M. Lin, and R. B. Wu, “Composite effects of reflections and ground bounce for signal line through a split power plane,” IEEE Trans. Adv. Packag., vol. 25, May 2002, pp.297-301.
[22] J. P. Berenger, “A perfectly matched layer for free-space simulation in finite-difference computer codes,” submitted to Annales Telecommunications, 1994.
[23] T. L. Wu, Y. H. Lin, J. N. Hwang, J. J. Lin, “The effect of test system impedance on measurements of ground bounce in printed circuit boards,” IEEE Trans. Electromagn. Compat., vol. 43, pp. 600-607, May 2001.
[24] J. N. Hwang, T. L. Wu, “The bridging effect of the isolation moat on the EMI caused by ground bounce noise between power/ground planes of PCB,” Electromagnetic Compatibility, 2001. EMC. 2001 IEEE International Symposium on , Volume: 1, pp. 471-474 , 13-17 Aug. 2001.
[25] T. Sudo, Y. Ko, S. Sakaguchi, T. Tokumaru, “Electromagnetic radiation and simultaneous switching noise in a CMOS device packaging,” Electronic Components and Technology Conference, , pp. 781-785, 21-24 May 2000.