本論文的第一部分我們設計了一個可變長度編碼和固定長度編碼的轉換介面，可適用於H.263的多重符號編碼解碼器。此轉換介面可以避免可變長度的缺點，並保留它的優點。此編碼解碼器會將可變長度編碼轉換成固定長度編碼的封包，進而在硬體上解碼時平行處理，提升速度。此轉換介面可將其他符號嵌入至固定長度封包內的冗餘位元，減低固定長度封包之低壓縮率的問題。
本論文的第二部分我們設計一個前一部份編碼解碼器的可合成Verilog碼產生器，可以產生不同模式的多重符號編碼解碼器。此程式碼產生器可依不同的成本需求或編碼位元率限制，輸入設定參數，即可產生合適的可合成多重符號編碼解碼器。

The first topic of this thesis is to carry out a multi-symbol codec (encoder-decoder) design for interfacing variable-length and fixed-length data conversion of H.263. The poor memory efficient of the variable-length can be avoided while its advantages can be reserved. The proposed codec converts variable-length symbols to fixed-length packets which can be decoded parallelly. The basic idea is to encode extra symbols in the redundant bits of the fixed-length packets. This encoding scheme relaxes the intrinsic poor compression rate of the prior fixed-length data codec.
The second topic is a synthesizable Verilog code generator for the mentioned multi-symbol codec. According to different requirements and constraints of encoding bit rate, the generator can provide several different kinds of encoding modes by selecting proper parameters. Each codec generated by the generator is synthesizable by thorough simulations.

摘要 i
Abstract ii
目錄 iii
圖目錄 v
表目錄 vii
第一章 簡介 1
1.1 前言 1
1.2 文獻探討 2
1.3 論文動機 3
1.4 論文大綱 4
第二章 適用於H.263之多重符號編碼解碼器 5
2.1 簡介 5
2.2 多重符號編碼解碼演算法 6
2.2.1 3-1多重符號編碼演算法 8
2.2.2 3-1多重符號解碼演算法 10
2.3 多重符號編碼解碼演算法之實作 12
2.3.1 3-1多重符號編碼器實作 14
2.3.2 3-1多重符號解碼器實作 16
2.4 晶片佈局與模擬結果 18
2.4.1 晶片佈局 18
2.4.2 3-1多重符號編碼器模擬結果 19
2.4.3 3-1多重符號解碼器模擬結果 20
2.5 晶片量測結果與討論 21
2.5.1 晶片量測結果 22
2.5.2 討論 24

第三章 適用於多重符號編碼解碼器之可合成Verilog程式碼產 生器………………………………………………………..28
3.1 簡介 28
3.2 架構與分析 28
3.2.1 解碼器實作 29
3.2.2 機率與壓縮效能分析 30
3.2.3 使用者圖形介面 33
3.3 佈局後模擬與比較 34
3.4 討論 45
第四章 結論與相關成果 46
參考文獻 47

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