本論文包含兩個主題，第一個主題是介紹一低功率雙緣觸發正反器。第二個主題為介紹一符合DVB-H 之正交分頻多工解調器。
低功率雙緣觸發正反器為一利用多臨界電壓電晶體技術所設計之低功率、高速度之正反器。低臨界電壓電晶體雖然會導致漏電流，卻因為可供應大輸出電流，故適合成為驅動電路。並搭配高臨界電壓電晶體之低漏電流特性，適合栓鎖資料，即可整合而構成單一栓鎖器雙緣觸發正反器，達到低功率、小面積和高速的設計。
本論文之另一主題為適用於DVB-H 之正交分頻多工解調器，其接收來自於前端的射頻訊號，且經過類比數位轉換器量化之數位訊號。然後將此數位訊號傳送到DVB-H 解調器做頻率、時間的校準和通道估測，此解調器包含了五個主要部分：符元時間同步、載波頻率偏移補償、快速傅立葉轉換、分散性領航訊號偵測和通道補償。

This thesis includes two topics. The first one is a low-power double-edge triggered flip-flop.The other is a orthogonal frequency division multiplex (OFDM) demodulator compliant with the Digital Video Broadcasting Handheld (DVB-H).
Low-power double-edge triggered flip-flop (DETFF) is based on multi-Vth transistors technique. Since low threshold voltage transistors are able to generate large leakage current, they are suitable to drive big loads. By contrast, high threshold voltage transistors are more appropriate to latch data due to their low leakage. Therefore, a single latch double-edge triggered flip-flop utilizing multi-Vth transistors can be a low power and high speed design without paying the price of large area.
The proposed OFDM demodulator is compliant with the DVB-H standard. The received DVB-H signal is processed by an RF front-end and the following analog-to-digital converter. Then, the digital signal is fed into the demodulator to adjust and calibrate the frequency, timing offset and channel estimation. The proposed DVB-H demodulator is mainly composed of five blocks : symbol timing synchronization block, carrier frequency offset compensation block, fast Fourier transform block, scatter pilot detection block and channel compensation block.

致謝...........................................................................................i
摘要..........................................................................................ii
Abstract .................................................................................iii
目錄.........................................................................................iv
圖目錄....................................................................................vii
表目錄......................................................................................x
第一章 前言與簡介................................................................1
1.1 前言...................................................................................1
1.2 文獻探討...........................................................................2
1.2.1 低功率雙緣觸發正反器...............................................2
1.2.2 適用於DVB-H 之正交分頻多工解調器......................3
1.3 論文大綱...........................................................................4
第二章 低功率雙緣觸發正反器............................................6
2.1 簡介...................................................................................6
2.2 電路架構與原理說明.......................................................7
2.2.1 多臨界電壓電晶體.......................................................7
2.2.2 雙緣觸發正反器電路設計.........................................10
2.2.3 整體晶片電路設計.....................................................17
2.3 電路模擬結果................................................................20
2.4 晶片量測結果與討論....................................................24
2.4.1 晶片佈局圖和照像圖.................................................24
2.4.2 晶片量測結果與波形圖.............................................25
2.4.3 量測結果討論.............................................................27
第三章 適用於DVB-H 之正交分頻多工解調器.................29
3.1 簡介................................................................................29
3.2 DVB-H 系統實體層原理...............................................30
3.3 DVB-H 接收機解調器架構與原理...............................33
3.3.1 符元時間同步.............................................................34
3.3.2 載波頻率偏移補償.....................................................35
3.3.3 快速傅立葉轉換.........................................................38
3.3.4 分散性領航訊號偵測.................................................38
3.3.5 通道補償.....................................................................40
3.4 整體系統架構實現........................................................44
3.5 模擬結果與預計規格....................................................45
3.5.1 通道估測模擬.............................................................45
3.5.2 整體晶片模擬結果.....................................................48
第四章 結論與成果..............................................................53
參考文獻...............................................................................55

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