本論文包含兩個主題。第一個主題介紹一個以直線漸近法為基礎的超低功率直接數位頻率合成器 (direct digital frequency synthesizer, DDFS) 架構及電路實作。第二個主題則以第一個主題的架構，實現一具誤差補償的低功率直接數位頻率合成器。
使用非線性數位類比轉換器 (nonlinear digital-to-analog converter, nonlinear DAC) 可以簡單逼近並實現弦波方程式，取代了以往使用ROM方式的相位到振幅轉換電路以及線性數位類比轉換器。同時，也有效地減少功率消耗與硬體的複雜度。上述DDFS加入誤差補償設計後，更能大幅提高合成訊號的無寄生動態範圍 (spurious-free dynamic range, SFDR)。

This thesis includes two topics. The first one is the architecture as well as the circuit implementation of an ultra low-power direct digital frequency synthesizer (DDFS) based on the straight line approximation. The second one is the circuit implementation of the low-power DDFS with an error compensation.
The proposed approximation technique replaces the conventional ROM-based phase-to-amplitude conversion circuitry and the linear digital-to-analog converter with a nonlinear digital-to-analog converter (DAC) to realize a simple approximation of the sine function. Thus, the overall power dissipation as well as hardware complexity can be significantly reduced. Besides, by adding the error compensation, the spurious-free dynamic range (SFDR) of the synthesized output signal can be raised drastically.

摘要……………………………………………………………………….i
Abstract ii
第一章 簡介 2
1.1 直接數位頻率合成器研究動機 2
1.2 具誤差補償之直接數位頻率合成器研究動機 2
1.3 論文目的 2
1.4 論文大綱 2
第二章 利用非線性數位類比轉換器實現超低功率直接數位頻率 合成器 2
2.1 簡介 2
2.2 原理概述 2
2.3 架構說明 2
2.3.1 使用非線性數位類比轉換器的直接數位頻率合成器架構 2
2.3.2 相位累加器 2
2.3.3 非線性數位類比轉換器架構 2
2.4 電路模擬與量測 2
2.4.1 控制電路輸出 2
2.4.2 相位累加器輸出 2
2.4.3 非線性數位類比轉換器輸出 2
2.4.4 佈局後模擬波形與結果 2
2.4.5 晶片佈局圖 2
2.4.6 晶片照相圖 2
2.4.7 晶片量測結果 2
2.4.8 晶片量測討論 2
第三章 利用非線性數位類比轉換器實現具誤差補償的低功率直 接數位頻率合成器 2
3.1 概論 2
3.2 取樣數對SFDR的分析 2
3.3 分割段數對SFDR的分析 2
3.4 加上誤差補償後對SFDR的分析 2
3.5 具誤差補償的直接頻率合成器架構 2
3.6 具誤差補償的直接頻率合成器之頻率控制 2
3.7 其他影響直接頻率合成器速度之要素 2
3.8 具誤差補償的直接頻率合成器之模擬結果 2
3.9 具誤差補償的直接頻率合成器之預計規格與佈局圖 2
第四章 結論 2
參考文獻 2

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