目前一般提供的算數計算模組仍以實數域上的為主，然而有限場算術運算﹐也廣泛應用在各種密碼機制和通訊系統的通道編碼中，譬如有限場常數乘法在新一代的密碼系統AES(Advanced Encryption Standard)和里德-所羅門碼(Reed-Solomon code)的編碼過程都會用到•本篇論文實作了一個有限場中常數矩陣乘法運算的電路合成器，能針對各種有限場矩陣運算﹐進行面積�速度效能之最佳化﹐主要是經由尋找所有位元布林函數的共用項﹐有效率地產生化簡後的電路﹐可以獲得比純粹用SYNOPSYS邏輯化簡更好的合成效果。

The arithmetic operations in most digital system are in the conventional binary number systems. However, the finite field arithmetic has also been widely used in applications of cryptography and communication channel coding. For example, finite field constant multiplication is applied to the advanced encryption standard (AES) and in the Reel-Solomon code. In this thesis, we develop a synthesizer that can automatically generate optimized gate-level netlists for constant matrix multiplication in Galois Field GF(2^n). The logic minimization is based on the a new common-factor elimination (CSE) algorithm that can efficiently finds the shared common factors among all the bit-level Boolean equations. Both the area and speed performance are considered during the logic optimization process. Experimental results show that the synthesized circuits have better area and/or speed performance compared with those obtained using Synopsys logic synthesis tools.

第一章 緒論 1
1.1研究背景及目的 1
1.2方法概述 2
1.2.1 問題的形式 2
1.2.2 邏輯閘共用的負作用 3
1.3內容大綱 4

第二章 相關基礎 5
2.1相關數學略述 5
2.1.1基底 5
2.1.2元素的表法 7
2.2文獻探討 7
2.2.1 xtime作法 7
2.2.2橫向起始法 9
2.2.3 LFSR的方法 12
2.2.4 相關議題在實數系 14
2.2.5 Synopsys的作法 14

第三章 實作 15
3.1 組合化簡 15
3.1.1縱向起始法 15
3.1.2橫向與縱向的討論 19
3.1.3 二迴合式 22
3.1.4 共用項的選擇 25
3.1.4.1取有最大漢明指數行對 25
3.1.4.2取具有最小行標關連性者 26
3.1.4.3取【1】總數最少行對 27
3.1.4.4考量具次高漢明指標的行對 27
3.2 元件對映 28
3.3 效能考量 29

第四章 實驗 33
4.1 應用 33
4.2 程式規格 34
4.2.1程式的輸入 35
4.2.1.1 XOR方程組 35
4.2.1.2 常數矩陣 35
4.2.2程式的輸出 36
4.2.2.1 架構層級的基本效能 36
4.2.2.2 硬體描述語言Verilog碼 37
4.3實驗結果 37
4.3.1 Synopsys合成環境的設定 37
4.3.2 一個字組的例子 38
4.3.3 內積式的例子 40
4.3.4 線性區塊編碼器的例子 41
4.3.5 常數矩陣的例子 43
4.4實驗討論 45

第五章 結論 50
5.1 總結 50
5.2 進一步研究 51
5.2.1 一般化比較邏輯合成的效果 51
5.2.2 自建XOR cell 52
5.2.3 考量元件擺置的效應 52
5.2.4 理想目標 53
5.2.5 交付標的 55

參考文獻

附錄
合成器輸出的測試檔範例
合成器輸出的閘級碼範例
合成器輸出 §4.3.2例子的可合成碼
合成器輸出 §4.3.3例子的可合成碼

[1] SYNOPSYS Design Compiler Reference Manual：Optimization and Timing Analysis, v2003.06

[2] Advanced Encryption Standard(AES)，Federal Information Processing Standards Publication 197，November 26，2001；AES Proposal：Rijndael, J. Daemen, V. Rijmen, 1999

[3] C. Paar. Efficient VLSI Architectures for Bit-Parallel Computation in
Galois Fields. PhD thesis, Institute for Experimental Mathematics, University
of Essen, 1994. English Translation.

[4] C. Paar , A New Architecture for a Parallel Finite Field Multiplier with Low Complexity Based on Composite Fields, IEEE Transactions on Computers, July 1996, vol 45, p856-61

[5] C. Paar , Optimized arithmetic for Reed-Solomon encoder, IEEE International Symposium on Information Theory, 1997, page 250

[6] C. Paar, P. Fleischmann, P. Roelse , Efficient Multiplier Architectures for Galois Fields GF(24n) , IEEE Transactions on Computers, February 1998, vol 47, p162-70

[7] S. Lin，D. J. Castello，“ Error control coding，Fundamentals and applications ”，Premtice-Hall，1983.

[8] F. J. M. Williams，N. J. A. Sloane，“The theory of error correcting codes”， North-Holand，1977.

[9] M. Potkonjak，M. B. Srivastava and A. P. Chandrakasan，“ Multiple constant multiplications：efficient and versatile framework and algorithms for exploring common subexpression elimination，” IEEE Trans. Computer-Aided Design，vol. 15，NO. 2，Feb. 1996，pp. 151 - 161.

[10] R. Pasko，P. schaumont，V. Derudder，S. Vernalde and D. Durackova，“ A new algorithm for elimination of common subexpressions ”，IEEE Trans. Computer- Aided Design，vol. 18，NO. 1，Jan. 1999，pp. 58 - 68.

[11] Reed Solomon Codes，J. Sylvester，January 2001.

[12] X. Zhang and K. K. Parhi，“ Implementation approaches for the Advanced Encryption Standard algorithm，” IEEE Circuits and Systems Magazine，Vol. 2， Fourth Quarter 2002，pp. 24 - 46