一個改進的低面積6-bit 3.3V逐步逼近管線式類比數位轉換器(SAR pipelined ADC)被提出，我們針對內部的3-bit類比數位轉換器以改進的threshold inverter quantization(TIQ)技術及類似快閃式逐步逼近類比數位轉換器的選擇機制來完成，藉由此提出的TIQ方法，可去除一般ADC所需要的參考電壓產生器及後端編碼器以減少面積的消耗，此外藉由flash-like SAR ADC選擇機制則可使得此ADC仍操作在高速。在multiplying digital to analog converter(MDAC)中的新3-bit DAC是以電壓模式操作，且只由調整的MOS電晶體來完成每個DAC階梯波的電壓準位，免除了電阻和電容的使用。藉由此種方法，此新DAC的面積可減小，結合提出的新3-bit ADC和3-bit DAC。則可設計出改進的6-bit低面積的ADC。藉由TSMC2P4M 0.35um CMOS製程，此面積低於0.017mm ，實驗結果顯示其功率消耗為3.77mW，取樣頻率為160MS/S，DNL為 0.344，INL為 0.74。

A improved less area 6-bit 3.3V SAR pipelined ADC is proposed. In this work, a 3-bit ADC is designed by the improved TIQ technology and flash like SAR ADC selection scheme. With the proposed TIQ method, it cancels the reference voltage generators and the backend encoders to reduce the area cost, besides the flash-like SAR ADC selection scheme makes the ADC still operate at high speed. The new 3-bit DAC in the MDAC is completed only by MOS transistors which channel widths and lengths are only adjusted to form each DAC output-voltage levels rather than using of resisters and capacitors in voltage mode. By the method, the area of the new DAC is reduced. By combining the proposed 3-bit ADC with the proposed 3-bit MDAC, an improved 6-bit ADC with less area is designed. By the TSMC 2P4M 0.35µm CMOS process, the area of the ADC is less than 0.017mm . The work shows that the power consuming is 3.77mW, the sampling rate is 160MS/S, the DNL is 0.344, and the INL is 0.74.

圖目錄
圖2.1 SAR ADC的基本觀念.................................10
圖2.2 SAR ADC的電路架構.................................10
圖2.3 An n-bit forward successive approximation A/D
converter.........................................11
圖2.4 Asynchronous flash converter schematic............12
圖2.5 Circuit diagram of the parallel-like architecture
based on the ISA-ADC circuit with 4-bit size......13
圖2.6 Chip microphotograph of the parallel-like ISA-ADC
chip..............................................14
圖2.7 Flash ADC的基本架構...............................15
圖2.8 Two types of transistor strings for a 2-bit flash
A/D converter.....................................16
圖2.9 2-bit PMOS transistor-string A/D converter .......16
圖2.10 Block diagram of the TIQ based 6-bit flash A/D
converter.........................................18
圖2.11 The comparison of the TIQ comparator and a
differential comparator ..........................18
圖2.12 DC analysis of the 63 TIQ comparator outputs......19
圖2.13 Logic level schematic of pre-encoder stage .......20
圖2.14 The optimized ’01’generator.....................20
圖2.15 Pre-encoder的各端點波形...........................21
圖2.16 Programmable logic array for encoding 4-level
input to 2-bit output.............................22
圖2.17 6-bit flash ADC which is used TIQ inverter to
lower power dissipation..........................23
圖2.18 Pipelined ADC的基本架構...........................24
圖2.19 Pipelined ADC的基本觀念圖.........................24
圖2.20 二進位加權比例的..................................25
圖2.21 R-2R based DAC....................................26
圖2.22 Charge redistribution converter...................27
圖2.23 由LSB先轉換的兩顆電容式DAC........................28
圖2.24 傳統由MSB先轉換的兩顆電容式.......................28
圖3.1 新提出的6-bit ADC的設計流程圖.....................30
圖3.2 (a)傳統的TIQ反相器，
(b)改進以適用於SAR選擇機制的TIQ反相器.............32
圖3.3 改進的TIQ反相器之節點波形.........................32
圖3.4 相對應於改進TIQ反相器之準位選擇器.................33
圖3.5 新提出的改進3-bit ADC.............................34
圖3.6 (a)傳統差動對，(b)將主動負載接至輸出端的差動對....35
圖3.7 op-amp的前端輸出增益級............................36
圖3.8 共源極輸出級......................................36
圖3.9 The concept of the beginning of the MOS DAC.......37
圖3.10 MOS DAC前導觀念之波形圖...........................37
圖3.11 Proposed 3-bit MOS DAC............................38
圖3.12 以新提出的DAC完成的MDAC...........................39
圖3.13 Trans-conductance latched comparator..............40
圖3.14 上半階梯波及下半階梯波的2-bit MOS DAC的輸出.......40
圖3.15 (a)NMOS電阻，(b)修正NMOS電阻以降低功率的方法......41
圖3.16 使用降低功率方法以修改DAC之輸出階梯波形...........42
圖4.1 The function blocks of pipelined ADC..............43
圖4.2 6-bit pipelined ADC的輸出波形.....................43
圖4.3 The DNL in TSMC 0.35um technology.................44
圖4.4 The INL in TSMC 0.35um technology.................44
圖4.5 The DNL in TSMC 0.18um technology.................45
圖4.6 The INL in TSMC 0.18um technology.................45
表4.1 This work與傳統ISA ADC的比較表....................46


目錄
第一章 導論................................................7
第二章 相關SAR ADC、flash ADC、DAC、pipelined ADC的
基本觀念與比較......................................9
2.1 逐步逼近式類比數位轉換器(SAR ADC)...................9
2.2 快閃式類比數位轉換器(Flash ADC)....................14
2.2.1 快閃式類比數位轉換器內的電阻串(The resister
string in flash ADC).............................15
2.2.2 比較器(Comparator)...............................17
2.2.3 預先編碼器(Pre-encoder)..........................19
2.2.4 二位元編碼器(Binary encoder).....................21
2.3 管線式類比數位轉換器(Pipelined ADC)................23
2.4 數位類比轉換器(DAC)................................24
2.4.1 電阻式DAC........................................25
2.4.2 電容式DAC........................................26
第三章 6-bit ADC電路設計.................................29
3.1 改進的3-bit TIQ SAR ADC(3-bit improved TIQ SAR
ADC).............................................31
3.2 放大器(Op-amp).....................................34
3.3 數位類比轉換器(DAC)................................36
3.3.1 降低功率的方法(The method for Power reducing)....39
第四章 結果與討論.........................................43
第五章 結論與未來發展.....................................49
參考資料..................................................51
附錄1 Layout圖...........................................54
附錄2 論文發表...........................................55

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