在微處理器的除錯技術中，使用電路擬真器(In-circuit Emulator)是相當常見的作法。使用ICE來對微處理器進行除錯具備了相當多的優點，包括相當小的硬體負擔、重複使用JTAG port的腳位等等。
目前系統單晶片的發展日趨成熟，系統單晶片中的微處理器的應用更是多樣化，各種類型的微處理器被廣泛地運用在嵌入式系統中。若要我們針對這些不同的嵌入式微處理器，運用其內嵌式電路擬真器來進行除錯的時，傳統上我們必須要使用不同的除錯軟硬體套件，這是一個相當不經濟的作法。而一個比較好的作法是設計出一個具有彈性的軟硬體控制模組，使得我們在對不同的微處理起進行除錯的時候可以使用同樣一套除錯軟硬體。
針對此，此篇論文將探討數種不同內嵌式電路擬真器的除錯架構，進而設計出一個參數化、模組化的電路擬真器控制軟硬體。我們藉由分析微處理器系統以及內嵌式除錯電路的架構分析出可重複使用的參數，使得我們在針對不同的處理器架構以及內嵌式除錯電路時，只需要改變參數就可以進行除錯的控制。我們藉由分析除錯控制軟硬體的功能，將各種功能獨立成不同的功能模組，一旦需要修改時只需要取代相關的模組即可。
透過參數化的設計，我們可以達到不修改除錯控制軟體的情況下重複使用此除錯控制軟體來對不同的微處理器系統進行除錯的控制。透過模組化的設計，在我們需要修改軟體時（例如移植到不同的作業系統或是使用不同的通訊介面）我們依然可以很輕易地修改我們的除錯控制軟體，快速的應用在不同的電路擬真器上。

The in-circuit emulator (ICE) is commonly adopted as a microprocessor debugging technique which features many advantages, such as low demand for hardware and repeatable use of the pins on the JTAG port. The development of system-on-chip technology has matured significantly in recent years. The microprocessors in system-on-chip designs have been applied in a variety of ways, and different microprocessors are being used in the embedded system. The traditional modus operandi of debug control, in which an ad hoc hardware/software package is required for each microprocessor, is not economical as far as programming and designing are concerned. Thus it is advisable to design a more flexible debug control hardware/software package which can fit into different embedded microprocessors with in-circuit emulators. This thesis reviews several types of embedded in-circuit emulator structure and comes up with a parameterized, modularized hardware/software package for controlling in-circuit emulators. An initial analysis of microprocessor systems and embedded debug circuits helps us to elicit reusable parameters so that we can achieve our desired debug control by simply adjusting parameters when we work on different microprocessor architectures and embedded debug circuits. An ensuing examination of the reusability and functionality of our designed debug control hardware/software enables us to group all the functions of our hardware/software package into different functional modules so that we can simply replace relevant functional modules on different microprocessor architectures and embedded debug circuits. The parameterized design allows us to use a single debug control software program on different microprocessor systems with the slightest change of parameter setting. The modularized model has the merit of minimizing our effort of debug control through module replacement when we need to adapt our software to a new environment (as when we want to use it on a different operating system or when we want to apply it to a different communication interface).

Chapter 1 Introduction
1.1 Background
1.2 Motivation
1.3 Proposed Approach
1.4 Research Contribution
1.5 Organization
Chapter 2 Related Work
2.1 Traditional Debug Method
2.1.1 Simulator
2.1.2 Rom Monitor
2.1.3 Logic Analyzer
2.1.4 In Circuit Emulator
2.2 Embedded Debug Architecture
2.2.1 Embedded Real Time Trace Circuit
2.2.2 Embedded In Circuit Emulator　
JTAG Architecture
Embedded ICE Circuit
2.2.3 Comparison
2.3 Debug Software
2.3.1 Category Of Debugger
2.3.2 GDB
2.3.3 PATH FINDER
Chapter3 Design Architecture Deliberation
3.1 Design Philosophy
3.2 Design Methodology
3.3 Parameter Analysis
3.3.1 Debug Action Analysis
3.3.2 Microprocessor Related Parameter
3.3.3 Embedded ICE Related Parameter
3.3.4 Parameter Summary
3.3.5 Debug action with parameter information
3.4 Modularization
3.4.1 Modularization Analysis
3.4.2 Graphic user Interface
3.4.3 Debugger
3.4.4 Parser
3.4.5 Control/Data Pattern Integration
3.4.6 Hardware Interface Encapsulation
3.4.7 H/W Interface Device Driver
3.5 Debug Control Hardware
3.5.1Hardware design analysis
3.5.2 Debug package format
Chapter4 Implement ation and Verification
4.1 Control Software Implementation
4.1.1 Graphical User Interface
4.1.2 Parser Implementation
4.1.3 Pattern Integration Module
4.1.4 Communication Module
4.2 Control Hardware Implementation
4.2.1 I/O Interface Module
4.2.2 Package Processing Module
4.2.3 TMS ROM Module
4.2.4 Serial Data Transfer
4.2.5 TDO Collector
4.2.6 TDO Memory
4.3 System Verification
4.3.1 Verification strategy
4.3.2 FPGA Verification Enviroment
Chapter 5 Application Example
5.1 PAC DSP System Architecture
5.2 On Chip Debug Circuit Design
5.3 Modified and Integrated Debugging System
5.4 System Verification
Chapter 6 Conclusion

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