現今電腦系統朝向高速、高頻、低電壓等趨勢發展，使得電源系統中地彈雜訊成為影響高速數位電路特性的主要因素。為了分析數位電路中地彈雜訊對訊號品質與電磁輻射的影響，發展一套正確及有效率的演算法是有必要的。本論文著重於兩部分探討，第一部份為發展演算法探討地彈雜訊的影響，我們以FDTD為基礎且發展了等效性電流源法、克希荷夫表面積分公式、二維狹縫修正之FDTD演算法等。第二部分為探討抑制地彈雜訊之方法，本論文提出低週期共平面之電磁能隙電源平面設計，經由實驗與模擬分析可發現，此結構設計具有寬頻地彈雜訊抑制效果與低輻射效率。

With the trends of fast edge rates, high clock frequencies, and low voltage levels for the high-speed digital computer systems, the ground bounce noise (GBN) or simultaneously switching noise (SSN) on the power/ground planes is becoming one of the major challenges for designing the high-speed circuits. In order to analyze the impact of the GBN on signal integrity (SI) and electromagnetic interference (EMI), an accurate and efficient modeling approach that considers the active devices and passive interconnects is required. This thesis focuses on two points. One is developing modeling approaches for analyzing the GBN effects, and the other is proposing solutions to reduce it. First, based on the FDTD algorithm several efficient modeling approaches including equivalent current-source method (ECSM), Kirchoff surface integral representation (KSIR), and slot-corrected 2D-FDTD are developed. After that, a power/ground-planes design for efficiently eliminating the GBN in high-speed digital circuits is proposed by using low-period coplanar electromagnetic bandgap (LPC-EBG) structure. Its extinctive behaviors of low radiation and broadband suppression of the GBN is demonstrated numerically and experimentally. Good agreements are seen.

Abstract i
Contents iii
List of Figures v
List of Tables xiii
Acronyms xiv

1. Introduction 1
1.1 Simultaneous Switching Noise (SSN) 2
1.2 High-speed Digital Circuit Design Trends and Challenges 3
1.3 Low-period Coplanar EBG Structure (LPC-EBG) 4
1.4 Objective and Organization of the Dissertation 5
2. FDTD Modeling Approach 7
2.1 Yee’s Algorithm 7
2.2 Numerical Stability 10
2.3 Absorbing Boundary Condition (PML) 10
2.4 Lumped Circuit Elements and Resistive Voltage Source 11
2.5 FDTD Time-stepping Process 12
2.6 Equivalent Current-Source Method (ECSM) 13
2.6.1 Theory of ECSM 13
2.6.2 Numerical Validity for ECSM 16
2.7 Near-to-Far-Field Transformation 19
2.7.1 Kirchoff Surface Integral Representation (KSIR) 19
2.7.2 Numerical and Experimental Validation 23
2.8 An Efficient 2D-FDTD Algorithm to Model Partitioned Power Planes 30
2.8.1 Theory and Algorithm for Slot-corrected 2D-FDTD 31
2.8.2 Numerical and Experimental Validations for
Slot-corrected 2D-FDTD 35
2.8.3 Incorporation of 1D Transmission Line Model with Slot-corrected 2D-FDTD 38
3. Impacts of SSN/GBN on SI and EMI 50
3.1 Chip-level Simultaneous Switching Noise 51
3.1.1 Parameters Discussion 52
3.1.2 Quiet Driver Effects on SSN 57
3.1.3 Summary 59
3.2 Board-level Ground Bounce Noise 60
3.2.1 Impacts of Through-hole-via Coupling on GBN 61
3.2.2 Impacts of Active IC on GBN 64
3.2.3 EMI Caused by GBN and Trace 69
3.2.4 Traditional Strategies to Reduce Board-level GBN 72
4. LPC-EBG Power/Ground-Planes Structure 76
4.1 Design Concept of the LPC-EBG Structures 76
4.2 1D-equivalent Circuit Model for Stopbnad Prediction 78
4.3 GBN Suppression 83
4.3.1 Frequency Domain 83
4.3.2 Time Domain 89
4.4 Radiated Emission 92
4.5 Impact of LPC-EBG Reference Planes on SI 94
4.5.1 Single-end and Differential Signals 94
4.5.2 Possible Solution of Embedded LPC-EBG Power Planes 97
4.6 Summary 99
5. Conclusion 100
Bibliography 102
Biography 109
Publication list 110

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