連續時間三角積分調變器(CTSDM)，它可以應用於無線通訊、照相或MP3播放器…等。可攜式電子產品成為主流後，低功率消耗的類比電路成為一大關鍵，因此本論文提出低功率消耗的連續時間三角積分調變器。

連續時間三角積分調變器包涵了一個由電阻電容式積分器所組成的三階迴路濾波器、一位元的量化器；藉由改良型Z轉換對應離散與連續時間之間的參數，來完成迴路濾波器雜訊轉移函數設計。

本論文使用TSMC 0.18μm CMOS 1P6M製程來實現低功率連續時間三角積分調變器，其電路的供應電壓為1V，取樣時間為12.8MHz，頻寬為200KHz，而超取樣率為32，動態範圍80dB，13bits的有效位元數，功率消耗為1.5mW。

關鍵字:全球通訊系統、低功率消耗、低供應電壓、連續時間、三角積分調變器。

Continuous-time sigma-delta modulator can be applied to wireless communications, photography and MP3 player. Portable electronics products became mainstream the design of a low power consumption analog circuit become important. Therefore, this paper presents a low power consumption continuous-time sigma-delta modulator.

The low-power continuous-time sigma-delta modulator includes one-bit quantizer and a third-order loop filter consisting of resistor-capacitor integrators. Through the modified Z-transform, the discrete time loop filter design is transformed to the continuous time loop filter design.

The proposed sigma-delta modulator used TSMC 0.18μm CMOS 1P6M standard process, and its supply voltage is 1V, oversampling ratio is 32, bandwidth is 200 KHz, effective number is 13bit, power consumption is 1.5mW.

Keywords: GSM, low power consumption, low power supply, continuous-time, sigma-delta modulator.

致謝 iii
中文摘要 iv
Abstract v
Contents vi
List of Figures ix
List of Tables xii
Chapter 1 Introduction 1
1-1Research Motivation 1
1-2Thesis Organization 5
Chapter 2 Fundamentals of Sigma-Delta Converter 7
2-1 Introduction 7
2-2 Signal Processing System of Sigma-Delta Modulator 7
2-3 The Basic Theory of Analog-to-Digital Converter 10
2-3-1 Oversampling Ratio (OSR) 10
2-3-2 Signal to Noise Ratio (SNR) 11
2-3-3 Signal to Noise and Distortion Ratio (SNDR) 12
2-3-4 Resolution 12
2-3-5 Dynamic Range (DR) 13
2-4 Sampling Theorem 14
2-5 Quantization Noise 16
2-6 Oversampling Technique 21
2-7 Noise Shaping Sigma-Delta Modulator 24
2-7-1 First-Order Sigma-Delta Modulator 28
2-7-2 Second-Order Sigma-delta Modulator 31
2-7-3 Higher-Order Sigma-Delta Modulator 34
2-8 Summary 37
Chapter 3 Basic Concept of Continuous-Time SDM Techniques 39
3-1 Introduction 39
3-2 Compared with Discrete-Time and Continuous-Time SDM 40
3-3 Implicit Anti-aliasing Filter in Continuous-time SDM 43
3-4 Clock Jitter 47
3-5 Effect of Excess loop delay 49
Chapter 4 The Proposal Low-Power Continuous-Time SDM 51
4-1 Introduction 51
4-2 The Proposed Third-Order CT Sigma-Delta Modulator 51
4-3 Implementation of Third-Order CT Sigma-Delta Modulator 53
4-4 Integrator 54
4-5 Quantizer 61
4-6 Constant-Gm Bias Circuit 63
4-7 Overall Performance of Continuous-Time SDM 65
4-7-1 Process Variation 67
4-7-2 Supply Voltage Variation 68
4-7-3 Temperature Variation 69
4-7-4 Dynamic Range 70
4-8 Summary 71
Chapter 5 The Experimental Results 73
5-1 Introduction 73
5-2 Test Setup 73
5-2-1 Power Supply Regulators 76
5-2-2 Reference (1V) Voltage generator 77
5-2-3 Input Terminal Circuit 78
5-3 The Die photomicrograph, Test Board, and Pin Configuration 79
5-4 Performances Evaluation of SDM 82
5-5 Summary 86
Chapter 6 Conclusions 87
Bibliography 88

[1] R.J. BAKER, “CMOS Circuit Design, Layout, and Simulation,” IEEE, Inc.,2005.
[2] O.A. Adeniran and A. Demosthenous, “Constant-resistance CMOS input sampling switch for GSM/WCDMA high dynamic range ΣΔ modulators,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 55, no. 11, pp. 3234-3245, Nov. 2008.
[3] M. Honarparvar, E. Najafi Aghdam, M. Shamsi, A. Zahedi and M. Zafaranchi, “A low power, high performance multi-mode delta-sigma ADC for GSM, WCDMA and WLAN standards,” The 2011 International Conference on Electronic Devices, Systems and Applications (ICEDSA2011), Computer Conference, Kualalumpur, Malaysia, April 2011.
[4] A. Rusu, D. R. L. Gonzalez, and M. Ismail, “Reconfigurable ADCs EnableSmart Radios for 4G Wireless Connectivity,” IEEE Circuits Devices Mag., vol.22, No. 3, pp. 6-11, May-June 2006
[5] D.A. Johns and K. Martin, “Analog Integrated Circuit Design.” John Wiley &Sons, Inc., 1997.
[6] K. Uchimura, “Oversampled A-to-D and D-to-A converters with multistage noise shaping modulators.” IEEE Trans. Acoust., Speech Signal Proc. 36, pp. 1899-1905, Dec. 1988.
[7] Y. Matsuya, K. Uchimura, A. Iwata, T. Kobayashi, M. Ishikawa and T. Yoshitome, “A 16-bit Oversampling A-to-D Conversion Technology Using Triple-Integration Noise Shaping,” IEEE J. Solid-State Circuits, Vol. SC-22, pp.921-929, December 1987.
[8] J. C. Candy, “Decimation for delta-sigma modulation” IEEE Trans. Commun.,
vol. 34, pp. 72-76, January 1986.
[9] S. Tewksbury, F. Meyer, D. Rollenhagen, H. Schoenwetter, T. Souders, “Terminology Related to the Performance of S/H, A/D and D/A Circuits”, IEEE Tran. on Circuits and Systems, Vol. CAS-25, No.7, pp 419-426, July 1978
[10] B. Razavi, “Principle of Data Conversion System Degsin” IEEE PRESS, 1995.
[11] S. Rabii; B. A. Wooley; “The Design of Low-Voltage, Low-Power Sigma-Delta Modulator,” Kluwer Academic Publisher, 1999.
[12] P. Aziz, H. Sorensen, and J. Spiegel, “An overview of sigma-delta converters,”IEEE Signal Processing Magazine, pp. 61-84, January 1996.
[13] F. Gerfers, M. Ortmanns, and Y. Manoli., “A design strategy for low-voltage low-power continuous-time ΣΔ A/D converters,” Proc. Design, Automation and Test Conf., pp. 361-368, 2001.
[14] J.A. Cherry and W.M. Snelgrove, “Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion.” Boston, MA:Kluwer, 1999.
[15] O. Shoaei, ”Continuous-time delta-sigma A/D converters for high speed applications,” PhD Thesis, Carleton University , 1995
[16] P.M.Chopp and A.A.Hamoui, “Analysis of clock-jitter effects in continuous-time ΔΣ modulators using discrete-time models,” IEEE Transactions on Circuits and Systems - I, vol. 56, no. 6, pp. 1134-1145, Jun. 2009.
[17] H.Chang, “A Simple Technique to Reduce Clock Jitter Effects in Continuous-Time Delta-Sigma Modulators,” IEEE International Symposium on Circuits and Systems, pp. 1870-1873, 2008
[18] J.A. Cherry and W.M. Snelgrove, “Excess loop delay in continuous-time delta-sigma modulators,” IEEE Trans. Circ. Syst. II, vol. 46, pp. 376-389, June, 1999.
[19] L. Samid and Y. Manoli, “A low power and low voltage continuous -time ΣΔ modulator,” IEEE International Symposium on Circuits and Systems, pp 4066-4069 ,2005.
[20] K.R. Laker, W.M.C. Sansen, “Design of Analog Integrated Circuits and System”, McGraw-Hill,1994.
[21] M. Dessouky and A. Kaiser, “Very low-voltage fully differential amplifier for switched-capacitor applications ”, Proc. IEEE Int. Symp. Circuits and Systems, vol. 5, pp.441 -444 2000
[22] M.H. Shen , L.H. Hung and P. Huang , “A 1.2 V fully differential amplifier with buffered reverse nested Miller and feedforward compensations”, Proc. IEEE ASSCC, pp.171 2006
[23] T.B. Cho, and P.R. Gray, “ A 10 b, 20 Msample/s, 35 mW pipeline A/Dconverter ” IEEE J. Solid-State Circuits, vol. 30, pp 166-172, 1995
[24] L. Sumanen, M. Waltari, and K. A. I. Halonen, “A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters”, Proc. ICECS, vol. 1, pp.32 -35 2000
[25] National Semiconductor, LM117/LM317A/LM317 3-Terminal Adjustable Regular Data Sheet, Nation Semiconductor, Inc., 1997.
[26] 鄭光偉,”一伏十位元CMOS 導管式類比數位轉換器”,國立台灣大學/電機工程學研究所/90/碩士/90NTU00442109.
[27] S.B. Kim , S. Joeres , R. Wunderlich and S. Heinen “A 2.7 mW, 90.3 dB DR Continuous-Time Quadrature Bandpass Sigma-Delta Modulator for GSM/EDGE Low-IF Receiver in 0.25 m CMOS” , IEEE J. Solid-State Circuits, vol. 44, no. 3, pp.891 -900 2009
[28] D.Y. Chang, S. Javvadi, C. Munoz, J. Abele, A. Hadiashar, et al., “A 1.2V Programmable ADC for a Multi-Mode Transceiver in 0.13 μm CMOS,” European Microwave Integrated Circuit Conference, pp. 151-154, October 2008.
[29] B. Jose, P. Mythili, J. Singh, J. Mathew, “A triple-mode sigma-delta modulator design for wireless standards”. Tenth Int. Conf. on Information Technology, Orissa, 2007, pp. 17– 20