連續時間三角積分調變器在生醫感測研究發展上扮演重要角色，適合用於監測基本的生命體徵(例如，呼吸、心跳)。但由於其生理訊號之強度非常微弱，且屬於低頻訊號，CMOS製程本身的閃爍雜訊源對欲觀察訊號受電路雜訊的影響會造成訊號在辨識上有一定程度的困難。本論文使用截波穩定調變技術來降低訊號頻寬內的雜訊，雜訊模擬採用時域雜訊分析方法，能同時在模擬電路整體效能時也把雜訊因素一併考慮進去。

在電路實現上，在有效頻寬約10Hz，取樣頻率為20.8kHz的情況下，其訊號雜訊失真比達到84.4 dB，其有效位元數達到13.7位元的解析度。使用台積電0.35μm 標準CMOS 2P4M製成完成，其晶片面積為 1.403 x 1.4 mm2。在3 V電源供應下，總功率消耗約為3.46 mW。

Continuous-time sigma-delta modulators play an important role in the development of biomedical sensors. It is suitable for monitoring of basic human vital functions (i.e., heartbeat and respiration). However, the physiological signal is very weak and it belongs to low-frequency range, the observed signals are strongly inter¬fered by the intrinsic flicker noise form CMOS transistors, which will cause a certain degree of difficulty in the identification.

This thesis describes the implementation of loop filter using a differential chopper-stabilized configuration to reduce the influence of flicker noise on sigma-delta modulator within the signal bandwidth. The noise analysis of this sigma-delta modulator is calculated by the time-domain noise simulation. This method can take the noise factors into account when analyzing the overall performance.

The proposed sigma-delta modulator is fabricated using TSMC 0.35μm 2P4M CMOS technology. The chip area is 1.403 x 1.4 mm2. With a sampling rate of 20.8 kHz, the modulator achieves 84.4 dB of the peak SNDR and ENOB is 13.7-bit within signal band¬width of 10Hz. It dissipates 3.46 mW under 3V supply voltage.

誌 謝 i
摘　要 ii
Abstract iii
Contents iv
List of Figures vii
List of Tables xi
Chapter 1 Introduction 1
1.1 Background 1
1.2 Literature Review 2
1.3 Research Motivation 3
1.4 Thesis Organization 4

Chapter 2 Fundamental Theorems of Sigma-Delta Modulator and Related Research 5
2.1 Overview of Analog-to-Digital Converters 5
2.2 Categories of Analog-to-Digital Data Converters 6
2.2.1 Nyquist-Rate ADC 7
2.2.2 Oversampling ADC 12
2.3 Oversampling with Noise-Shaping: ΔΣADC 16
2.3.1 Noise Shaping 17
2.3.2 ΔΣ Modulator 18
2.4 High-Order Sigma-Delta Modulator Architecture 23
2.4.1 Second-Order Sigma-Delta Modulator 23
2.4.2 Single-Loop High-Order Sigma-Delta Modulator 25
2.4.3 Cascade Sigma-Delta Modulator 27
2.5 Summary 28

Chapter 3 Noise Considerations and Method for 1/f Noise Reduction 29
3.1 Noise sources 29
3.1.1 Thermal Noise 30
3.1.2 Flicker Noise 32
3.1.3 Noise Model for MOSFET 33
3.2 Noise Analysis in the Time-Domain 34
3.2.1 Overview of Transient Noise Analysis 34
3.2.2 Modeling Time-Domain Noise Sources 35
3.3 Chopper Stabilization Technique 37
3.3.1 Basic Principle 37
3.3.2 Residual Offset 39
3.4 Summary 41

Chapter 4 System Architecture and Design 43
4.1 Proposed First-Order Sigma-Delta Modulator Utilizing Chopper-Stabilization Based Circuit Technique 44
4.2 Preamplifier 46
4.2.1 Fully Differential Folded-Cascode OPAMP 46
4.2.2 Continuous-Time Common-Mode Feedback (CMFB) 49
4.2.3 Wide-Swing Constant-Gm Bias Circuit 50
4.3 Post-amplifier 51
4.4 Quantizer 55
4.5 Non-overlapping Clock Generator 57
4.6 Synchronous Counter 58

Chapter 5 Experimental Implementation and Results 61
5.1 Design Flow 61
5.2 Layout and Pin Assignment 63
5.3 Circuit Simulation 65
5.3.1 Noise Analysis 65
5.3.2 Simulation Results 68
5.3.3 Comparison 73
5.4 Test Setup and Experimental Results 74
5.4.1 Measuring Environment 74
5.4.2 Power Supply Regulator 75
5.4.3 Measurement Results and Discussion 76
5.5 Summary 82

Chapter 6 Conclusions and Future Works 83
6.1 Conclusions 83
6.2 Future Works 84
Reference 85

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