隨著平面顯示器的尺寸越來越大，應用在顯示器上的電晶體所需要的電子遷移率(mobility)也必須越來越高，但是傳統的非晶矽薄膜電晶體的電子遷移率太低(<1 cm2/V•s)，因此擁有較高電子遷移率(1~20 cm2/V•s)的非晶金屬氧化物薄膜電晶體對於下一新時代的顯示器應用上很有潛力，且擁有許多優越的特性，所以近年來已經成為熱門的研究領域。
由於過去α-IGZO TFTs元件在源極與汲極的接觸面積非常大，無法確定電子走的路徑，所以使用via類型的元件，減少源極與汲極的接觸面積，較能確定電子走的路徑。在本論文中我們將分析研究改變元件閘極與汲極不同的重疊程度、主動層與源極或汲極的接觸面積大小與邊緣電場效應等不同結構下的電性。雖然α-IGZO TFTs有許多良好的優點，但它的電性卻會受到照光以及長時間電壓操作的影響。我們再將先前提到的這些結構去做可靠度研究，會探討閘極正偏壓、熱載子效應與閘極負偏壓且照光可靠度量測。
實驗結果顯示使用via類型的元件，經由萃取接觸電阻知道電子走的路徑大於光罩上的通道長度，且由不同的元件結構可以發現，在改變閘極與汲極不同的重疊程度時，不受閘極控制的一段主動層，如同會產生電阻的效應；若改變主動層與源極或汲極的接觸面積大小，在通道長度較短的熱載子效應，不論其接觸面積大小，在汲極端都會有接近的空乏長度；在邊緣電場效應區塊做閘極負偏壓且照光的可靠度量測，因為有電洞被捕獲，造成起始電壓(threshold voltage)向左飄移。

The higher mobility is needed for thin film transistor (TFT) mainly used to be applied in the larger size flat-panel displays (FPDs). The amorphous metal oxide TFT has mobility higher than 10 cm2/V•s and can substitute the poor mobility (<1 cm2/V•s) of traditional amorphous silicon TFT, which shows a great potential for the next generation. Due to the superior characteristics in amorphous metal oxide TFT, therefore, the amorphous metal oxide TFT has been studied extensively.
Usually, the source/drain with island type device has a large overlapped/contact area that we cannot determine the exact electron path. That the sample of inverted stagger α-IGZO TFTs with via type device has smaller contact area and can be estimated the electron path. In this thesis, the devices with different M1 overlaps etching stop layer (ESL) via distance, M2 α-IGZO contact size and the fringe field effect are investigated. Although the characteristics of α-IGZO TFTs have great performance, the electrical stability under illumination and long term bias stress are still a important issue to study before implement them into display. Thus, the devices with different structures that we mentioned previously are investigated the electrical reliability which are the negative bias stress of gate voltage, hot carrier stress effect and negative bias of illumination.
The electron path of via type is extracted by contact resistance which is greater than the distance between S/D via. Experiment results show that the increased offset between M1 and ESL via generates the resistance-liked effect in electrical characteristics. The hot carrier stress effect is independent of M2 α-IGZO contact size in short channel length devices and there are close depletion lengths in drain side. The negative bias stress of illumination is proceeded in the fringe field effect devices, which results a negative shift of threshold voltage due to the hole trapping.

論文審定書………………………………………………………………………………i
誌謝……………………………………………………………………………………ii
Abstract (Chinese)…………………………………………………………………..iii
Abstract (English)…………………………………………………………………… iv
Contents ………………………………………………………………………………..vi
Figures captions……………………………………………………………………....ix
Table caption ………………………………………………………………………...ixii
Chapter 1 – Introduction………………………………………………………………1
1.1 Amorphous Oxide Semiconductor Thin Film Transistors 1
1.2 Origin of High Electron Mobility 2
1.3 Why Use α-IGZO 3
Chapter 2 - Device fabrication and electrical characterization……………………8
2.1 Device fabrication 8
2.2 Electrical characteristics 8
2.2.1 The I-V transfer characteristics 8
2.2.2 The C-V transfer characteristics 11
Chapter 3 - Instruments and device parameter extraction…...………………….....15
3.1 Instruments and measurement setup 15
3.1.1 Instruments 15
3.1.2 Set up instruments for I-V 16
3.2 Device parameter extraction 16
3.2.1 Determination of the threshold voltage 16
3.2.2 Determination of the field-effect mobility 17
3.2.3 Determination of the subthreshold swing 18
3.2.4 Determination of on/off current ratio 19
Chapter 4 - Results and Discussion………………………………………………… 22
4.1 M1 overlaps etching stop layer (ESL) via Distance 22
4.1.1 M1 overlaps ESL via Distance in asymmetric structures 22
4.1.2 M1 overlaps ESL via Distance under positive gate bias stress 25
4.2 M2 α-IGZO contact size 25
4.2.1 Source/Drain series-resistance effects in α-IGZO TFTs 25
4.2.2 The hot carrier stress effect in α-IGZO TFTs 27
4.3 The fringe field effect 32
4.3.1 The structure of fringe field effect 32
4.3.2 The fringe field effect of negative gate voltage stress with illumination 32
Chapter 5 – Conclusion………………………………………………………………56
References……………………………………………………………………………...58

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