由於現今媒體通訊系統的快速發展，其系統的規模已經越來越複雜化，為了增進即時運算處理的能力並縮短系統研發的時間，系統架構的可重新組態能力成為一個重要的及彈性化的設計考量。本論文中所實現的可重新組態運算單元FMRPU是一微顆粒與多重組態內容的可重新組態運算單元，其設計針對高處理量及高資料平行度的應用處理。它包含了64個可重新組態邏輯陣列與16個轉接盒，並且透過三層的階層式互連網路來相互連結。另外為了避免過長的繞線路徑成為映射電路的效能瓶頸，設計了資料流轉接器來重新安排資料流。根據模擬分析的結果，此架構最長的繞線路徑在0.35製程下只需6.5 ns，可以有效率的結構成所要求的邏輯電路，在影像處理的移動估計(Motion Estimation)運算的比較與同類型架構相比效能增加了17%，以及在做其他訊號處理演算法時，也有優於同型架構的效能。

At present the scale of multimedia and communication systems has become more and more complicated due to the fast development of them. In order to improve the capability of real-time processing and shorten system development time, the ability to reconfigure system architecture becomes an important and flexible design consideration. In this thesis, we propose a reconfigurable processing unit, FMRPU, which is a fine-grain multi-context reconfigurable processing unit targeting at high-throughput and data-parallel applications. It contains 64 reconfigurable logic arrays, 16 switch boxes, and connects with each other via three hierarchical-level connectivities. To avoid the excessive routing path to be the bottleneck of mapped circuits, we design the data stream switch to rearrange data streams. According to the simulation results, the longest routing path of FMRPU only takes 6.5 ns at 0.35 processes, which is able to construct the required logic circuit efficiently. Compare with same kind devices in dealing with Motion Estimation operations, the performance is raise to 17% and is excellent to other same kind architectures in executing other DSP algorithms.

摘要 i
ABSTRACT ii
Contents iii
List of Figures v
List of Tables vii
Chapter 1 Introduction 1
1.1 The Development Background of Reconfigurable Computing 2
1.2 Logic resources of FPGA architecture 6
1.3 Reconfigurable Computing System 11
1.4 Motivation and Goal 13
Chapter 2 Survey 15
2.1 Features of reconfigurable architecture 15
2.2 Compilation environments for Reconfigurable Computing 19
2.3 Previour Work for Reconfigurable Computing 25
Chapter 3 Architecture of Fine-grain Multi-context Reconfigurable Processing unit .30
3.1 Basic Components of FMRPU 30
3.1.1 Logic Cell (LC) 32
3.1.2 Logic Bank (LB) 39
3.1.3 Logic Array (LA) 40
3.1.4 Switch Box (SB) 41
3.1.5 Data Stream Switch (DSS) 43
3.2 Interconnection network of FMRPU 44
3.2.1 Interconnection Function and Neighbor Set 45
3.2.2 Interconnection Network of LA 46
3.2.3 Hierarchical-level Interconnection Network of FMRPU 51
3.2.4 Methodology of Searching the Optimized Routing Path 59
3.3 Reconfiguration mechanism of FMRPU 73
3.3.1 Reconfiguration Architecture of FMRPU 77
3.3.2 Reconfiguration time of FMRPU 82
Chapter 4 Verification and Evaluation 85
4.1 Verification environment 86
4.2 Synthesis results 87
4.3 Performance and area analysis of FMRPU 89
4.4 Mapping to FMRPU 91
4.4.1 Motion Estimation for MPEG 93
4.4.2 Discrete Cosine Transform 98
4.4.3 Quantization ane Inverse Quantization 102
4.4.4 The mapping of FFT, FIR, IIR to FMRPU 103
4.5 Summary of physical implementation 109
Chapter 5 Conclusions and Future Work 113
Reference 115

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