由於傳統浮停閘快閃記憶體的在元件尺寸持續微縮下，此結構將面臨一些瓶頸，為了克服瓶頸因而衍生出兩種非揮發性記憶體結構：一種是SONOS非揮發性記憶體，另一種則是nanocrysatl（量子點）非揮發性記憶體。
在本論文中，主要在探討將記憶體元件製作在類似玻璃基板上的特性，利用SONOS非揮發性記憶體將與複晶矽薄膜電晶體互相整合的技術，進而研究具有奈米線之非揮發性記憶薄膜電晶體(Nonvolatile SONOS TFT memory with Nano-wire structure)的特性及記憶體特性。
在薄膜電晶體方面，我們利用ONO多層閘極介電質來調配閘極介電質的介電常數，在不減少薄膜厚度的情況下，提高閘極的控制能力；另一方面，我們同時利用奈米線在邊緣處的曲率半徑較小，在相同電壓下，有較大的電場之特性，製作出多通道奈米線的薄膜電晶體，可以有效的降低導通電壓(threshold voltage)，增加開關電流比(On/Off ratio)，較陡峭的次臨界導通斜率(subthreshold slope)，和更優良的元件驅動能力，其電性較一般標準結構的薄膜電晶體為好。
在記憶體方面，由於奈米線通道之元件具有較優越與較穩定的電晶體特性，便針對一條通道且其寬度為1μm與奈米線通道且其每條寬度為65nm之元件的記憶體特性作比較，可以明顯發現奈米線結構具有較大的記憶窗，且有比較高的寫入/抹除效率，主要是由於奈米線之記憶體元件具有分立奈米線，使得閘極環跨於通道時，形成環繞式的三向閘極(tri-gate)，閘極擁有較佳的控制能力，且閘極與通道形成多處稜角，此處有較強的電場分佈，使得電子較易透過FN-tunneling通過穿隧氧化層而儲存於氮化矽層的缺陷能階內，造成起始電壓的改變而擁有記憶體的特性，此技術將有機會被利用在系統面板上。
在可靠度方面,為了要克服Hard-to-Erase 的問題,在本文中提出新的操作機制, 採用Reset(負極FN)的方式找到一個新的基準點,將所有的Vt歸位.由此也可以證明Nanowire 可以克服Gate injection的問題。另外又針對的不同溫度下寫入/抹除的操作特性作更進一步的探討。
多層閘極奈米線薄膜電晶體有極大的潛力應用在面版上的系統整合，利用多層閘極介電質薄膜電晶體同時具有高效能驅動元件及非揮發性記憶體元件的特性，可以大幅的簡化製程步驟。

The conventional floating gate NVSM will suffer some limitations for continued scaling of the device structure. Therefore, the silicon-oxide-nitride-oxide-silicon (SONOS) and the nanocrystal nonvolatile memory devices, have been investigated to overcome the limit of the conventional floating gate NVSM.
For driving device application, we have used multilayer ONO gate dielectrics to make change the effective dielectric constant. The proposed TFT with ONO gate dielectrics have better gate control ability. On the other hand, nanowire has larger electric-field in the corner region at the same voltage. The SONOS-TFT with multiple nanowire channels have superior electrical characteristic, such as lower threshold voltage, higher On/Off ratio, steeper subthreshold slope, and superior driving ability.
The memory characteristic of standard SONOS-TFT, channel width of the device is 1μm, was compared with the nanowires SONOS-TFT, each channel width of the device is 65nm. The SONOS-TFT with multiple nanowires structure (NW SONOS-TFT) has good program/erase efficiency, retention, transfer characteristics and can suppress gate injection effectively. These characteristics are due to the larger electric field at the corner region and more number of corners. The NW SONOS-TFTs can be treated as high performance devices and also as high program/erase efficiency nonvolatile memory under adequate voltage range operation. In this thesis, the P/E characteristics at different temperatures will also be measured and discussed.
The fabrication of SONOS-TFTs with nano-wire channels is quite easy and involves no additional processes. Such a SONOS-TFT is there by highly promising for application in the future system-on-panel display applications.
The SONOS-TFTs combined the TFT and memory properties at the same time. Furthermore, the process flow is compatible with conventional poly-Si TFTs fabrication without additional process steps. Hence, the application of SONOS TFTs structure can reach the goal of system on panel (SOP) in the future.

Contents
Chinese Abstract………………...................................................................................I
English Abstract………………..................................................................................III
Contents……………….................................................................................................V
Figure Captions………………..................................................................................VIII
Chapter One – Introduction
1-1.Introduction of the Polycrystalline Silicon Thin-Film Transistor………………... 1
1-2.Introduction of Nonvolatile Memory Devices ………………............................ 3
1-2-1.The SONOS Nonvolatile Memory Devices ……………….......................................3
1-2-2. The Nanocrystal Nonvolatile Memory Devices …………………………………….6
1-4.References…………………………………………………………………………9
Figures 12
Chapter Two – Basic Mechanisms of thin film transistor and Nonvolatile Memory Device
2-1.Polycrystalline Silicon Thin Film transistor………………………………………16
2-1-1.Introction ……………………………………………………………………………………16
2-1-2.Apparatus …………………………………………………………………………………...20
2-1-3.Methods of Devices Parameter Extraction..…………………………………………………21
2-2.Nonvolatile Memory Devices…………………………………………………….23
2-2-1.Introdction …………………………………………………………………….23
2-2-2.Basic Program/Erase Mechanisms ………………………………………………………….26
2-2-3. Basic Reliability of Nonvolatile Memory Devices…………………………………………31
2-3. Basic Physical Characteristics of nanocrystal NVM…………………………….32
2-3-1.Quamtum confinement Effect…………………………………………………………………….32
2-3-2.Coulomb Blockade Effect………………………………………………………………………...32
2-4.Referances………………………………………………………………………...34
Figures………………………………………………………………………………...37
Chapter Three – Novel Nonvolatile SONOS-TFT Memory with Nanowire Structure
3-1.Motivation………………………………………………………………………...42
3-2.Device Fabrication………………………………………………………………..44
3-3.Results and Discussion……………………………………………………………47
3-3-1.The Physical Characteristic of SONOS-TFT with Multiple Nano-wire Channels………….47
3-3-2. The Electrical Characteristic of SONOS-TFT with Multiple Nano-wire Channels………..47
3-4.Summary I………………………………………………………………………...52
3-5.Referance………………………………………………………………………….53
Figures………………………………………………………………………………...54
Chapter Four –Non-ideal effect and temperature-dependent program/erase phenomenon under memory mode operation
4-1 Self-convergent property of the memory device
4-1-1.Motivation……………………………………………………………………..66
4-1-2.Experiment…………………………………………………………………….67
4-1-3. Result & Discussion……………………………………………………………68
4-1-4 Summary I…………………………………………………………………….71
4-2. Program/Erase characteristics at high temperature
4-2-1.Motivation……………………………………………………………………..72
4-2-2.Experiment…………………………………………………………………….73
4-2-3. Results and discussion…………………………………………………………..74
4-2-4. Summary II …………………………………………………………………...77
4-3.Referance……………………………………………………………….………...78
Figures………………………………………………………………………………...79

Chapter Five – Conclusion
Conclusion……………………………………………………………….…….……...91

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