積體電路中，常見的電子元件包括高功率元件、微處理器及記憶體等，主要是由金氧半場效電晶體所組成。因其具備了低製造成本、較低的功率損耗且易微縮化等優點。然而在傳統電晶體的尺寸持續微縮下，會面臨到短通道效應，如：punch-through、DIBL，甚至會有直接穿隧的閘極漏電等問題發生，這不但降低了閘極的控制能力且也增加元件本身的功率消耗。在45奈米以下的互補式金氧半場效電晶體技術，因嚴重的閘極漏電，所以使得傳統的二氧化矽介電層和多晶閘極被氧化鉿絕緣層/氮化鈦閘極電晶體取而代之。在此篇論文，我們利用了分離式電容-電壓、快速電流-電壓及電荷汲取等不同的量測方法來分析電晶體的特性以及物理機制的探討。從實驗結果可知，元件在閘極端施加交流脈衝時的劣化情形，會比直流偏壓還要更嚴重；而在閘極端給交流脈衝下，隨著溫度的上升，對n型金氧半場效電晶體而言，由於在高溫時有電子發射，所以使得元件的劣化情形變得較不嚴重；相反的，對p型金氧半場效電晶體，因其劣化由負偏壓溫度不穩定性的機制主導，隨著溫度的增加，元件的劣化情形更嚴重。對應於操作在熱載子電應力的不同閘極偏壓下，將會由不同的熱載子及載子補獲特性效應主導。對於不同金屬閘極鈦濃度進行負偏壓溫度不穩定性的閘極偏壓電應力測試，實驗結果顯示不同鈦濃度的金屬閘極將影響元件的基本參數。而這些現象與氮擴散到高介電閘極層與通道介面有關。

Electronic devices such as high power devices, microprocessors and memories in integrated circuit are primarily composed of metal-oxide-semiconductor field effect transistors (MOSFETs), due to the advantages of low cost, low power consumption and easy to scale down. However, the aggressively scaled conventional MOS devices have suffered remarkable short channel effects such as drain induced barrier lowering, punch-through, and direct-tunneling gate leakage. These problems not only lower the gate controllability but also increase the standby power consumption. Because the SiO2 dielectric and poly-gate are improper for CMOS application below 45 nm technology node due to the critical gate leakage current. Therefore, we investigate the electrical characteristics and physical mechanisms of MOSFETs with HfO2/TixN1-x gate stacks by using split C-V, pulsed Id-Vg, and charge-pumping techniques. The experimental results indicate that dynamic stress is more serious than static stress, and hot-carrier effect corresponding to different gate stress biases demonstrate distinct dominant degradation behaviors and the charge-trapping phenomenon. Furthermore, different concentration of titanium in TiN metal gate significantly affect device characteristics associated with the amount of nitrogen diffusion from the metal gate to high-k bulk and the SiO2/Si interface layer.

論文審定書 i
Abstract (Chinese) ii
Abstract (English) iii
Contents iv
Figure Captions vii

Chapter 1 Introduction
1.1 Introduction 1
1.2 Motivation 3
1.3 Semiconductor Parameter Analyzer Instruments 4

Chapter 2 Parameter Extraction and Measurement Technique
2.1 Method of Device Parameter Extraction 13
2.1.1 Determination of the threshold voltage 13
2.1.2 Determination of the subthreshold swing 14
2.1.3 Determination of the low-field effect mobility 14
2.2 Principle of Measurement Technique 15
2.2.1 Charge-Pumping Measurement 15
2.2.2 Split C-V Technique 18

Chapter 3 Dynamic PBS Frequency Dependent Charge Trapping Characteristic of high-k/metal gate n-MOSFETs
3.1 Introduction 28
3.2 Experiment 29
3.3 Results and Discussion 30
3.4 Summary 32

Chapter 4 Temperature Dependence on Dynamic PBS and NBS Degradation for n-type and p-type MOSFETs
4.1 Introduction 38
4.2 Pulsed I-V measurement method 39
4.3 Experiment 40
4.4 Results and Discussion 41
4.5 Summary 43

Chapter 5 Gate-Induced Drain Leakage Current variation of high-k/metal Gate n-MOSFETs induced by Hot Carrier Effect
5.1 Introduction 49
5.2 Experiment 51
5.3 Results and Discussion 52
5.4 Summary 56

Chapter 6 Impact of TiXN1-X gate on NBTI Degradation for high-k/metal gate p-MOSFETs
6.1 Introduction 64
6.2 Mechanism of Negative Bias Temperature Instability 65
6.3 Experiment 66
6.4 Results and Discussion 67
6.5 Summary 69

Chapter 7 Conclusion
7.1 Conclusion 75

References 78

Chapter1
[1.1] P. P. Wang, “Device characteristics of short-channel and narrow-width MOSFETs,” IEEE Trans. Electron Dev., ED-25, pp. 779-786 (1978).
[1.2] R. H. Dennard, F. H. Gaensslen, H. Yu, V. L. Rideout E. Bassons and A. R. LeBlanc, “Design of ion-implanted MOSFETs with very small physical dimensions,” IEEE J. Solid-State Circuits, SC-9, pp. 256-268 (1974).
[1.3] S.M.SZE, “Physics of Semiconductor Devices,” WILEY-INTERSCIENCE, Third Edition, Hoboken, New Jersey, 2007.
[1.4] Dieter K. Schroder, and Jeff A. Babcock, “Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing,” J. Appl. Phys., vol. 94, pp. 1-18 (2003).
[1.5] M. A. Alam, and S. Mahapatra, “A comprehensive model of PMOS NBTI degradation,” Microelectronics Reliability, vol. 45, pp. 71-81 (2005).
[1.6] C. S. Lu, H. C. Lin and Y. J. Lee, “Improvement of negative-bias-temperature instability in SiN-capped p-channel MOSFETs using ultrathin HfO2 buffer layer,” J. Electrochem. Soc., vol. 154, pp. H1036-H1040, (2007).

Chapter2
[2.1] A. Ortiz-Conde, F. J. Carcia Sanchez, J. J. Liou, A. Cerdeira, M. Estrada and Y. Yue, “A review of recent MOSFET threshold voltage extraction methods,” Microelectronics Reliability, vol. 42, pp. 583-596 (2002).
[2.2] J. S. Brugler and P. G. A. Jespers, “Charge pumping in MOS devices,” IEEE Trans. Electron Dev. ED-16, pp. 297-302 (1969).
[2.3] P. Heremans, J. Witters, G. Groeseneken, H.E. Maes, “Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation”, IEEE Trans. Electron devices, Vol. 36, pp. 1318 (1989).
[2.4] M.B. Zahid, R. Degraeve, M. Cho, L. Pantisano, D.R. Aguado, J. Van Houdt, G. Groeseneken, M. Jurczak, “Deffect profiling in the SiO2/ Al2O3 interface using Variable Tcharge-Tdischarge Amplitude Charge Pumping (VT2ACP)”, IEEE International Reliability Physics Symposium, pp. 21-25 (2009).
[2.5] Takagi S., Toriumi A, “On the university of inversion layer mobility in Si MOSFETs: part I-effects of substrate impurity concentrate,” IEEE Trans. Electron Dev., vol. 41, pp. 2357-2362 (1994).
[2.6] Takagi S., Toriumi A, “On the university of inversion layer mobility in Si MOSFETs: part II-effects of surface orientation,” IEEE Trans. Electron Dev., vol. 41, pp. 2363-2368 (1994).
[2.7] A. G. Sabnis and J. T. Clemens, “Characterization of the electron mobility in the inverted (100) Si surface,” IEEE Int. Electron Dev. Meet., pp 18-21 (1979).
[2.8] S. C. Sun and J. D. Plummer, “Electron mobility in inversion and accumulation layers on thermally oxidized silicon surface,” IEEE Trans. Electron Dev., ED-27, pp. 1497-1508 (1980).

Chapter3
[3.1] Y. Kim, G. Gebara, M. Freiler, J. Barnett, D. Riley, J. Chen, K. Torres, J. E. Lim, B.Foran, F. Shaapur, A. Agarwal, P. Lysaght, G. A. Brown, C. Young, S. Borthakur, H. J. Li, B. Nguyen, P. Zeitzoff, G. Bersuker, D. Derro, R. Bergmann, R. W. Murto, Alex Hou, H. R. Huff, E. Shero, C. Pomarede, M. Givens, M. Mazanec, and C. Werkhoven, “Conventional n-channel MOSFET devices using single layer HfO2 and ZrO2 as high-k gate dielectrics with polysilicon gate electrode”, in IEDM Tech. Dig., pp. 455 (2001).
[3.2] C. Hobbs, H. Tseng, K. Reid, B. Taylor, L. Dip, L.Hebert, R. Garcia, R. Hegde,
J.Grant, D. Gilmer, A. Franke, V. Dhandapani, M. Azrak, L. Prabhu, R. Rai, S. Bagchi, J. Conner, S. Backer, F. Dumbuya, B. Nguyen, and P. Tobin, “80 nm Poly-Si Gate CMOS with WOz Gate Dielectric” in IEDM Tech. Dig., pp. 651(2001).
[3.3] M. Fischetti, “Scaling MOSFETs to the limit: A physicist’s perspective,” J. Comput. Electron., 2, 73 (2003).
[3.4] G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C. Parthasarathy, E. Vincent, and G. Ghibaudo, “Review on High-k Dielectrics Reliability Issues”, IEEE Trans. Device And Materials Reliability, 5, 5(2005).
[3.5] S. Zafar, A. Callegari, E. Gusev, and M. V. Fischetti, “Charge trapping related threshold voltage instabilities in high permittivity gate dielectric stacks”, J. Appl. Phys., 93, 9298(2003).
[3.6] E. P. Gusev, D. A. Buchanan, E. Cartier, A. Kumar, D. DiMaria, S. Guha, A. Callegari, S. Zafar, P. C. Jamison, D. A. Neumayer, M. Copel, M. A. Gribelyuk, H. Okorn-Schmidt, C. D’Emic, P. Kozlowski, K. Chan, N. Bojarczuk, L-A. Ragnarsson, R. Ronsheim, K. Rim, R. J. Fleming, A. Mocuta, and A. Ajmera, “Ultrathin high-κ gate stacks for advanced CMOS devices,” in International Electron Devices Meeting (IEDM) Technical Digest, pp. 451-454 (2001).
[3.7] A. Kerber, E. Cartier, L. Pantisano, R. Degraeve, T. Kauerauf, Y. Kim, A. Hou, G. Groeseneken, H. E. Maes, and U. Schwalke, “Origin of the Threshold Voltage Instability in SiO2/HfO2 Dual Layer Gate Dielectrics”, IEEE Electron Device Lett., 24, 87 (2003).
[3.8] H. R. Harris, R. Choi, J. H. Sim, C. D. Young, P. Majhi, B. H. Lee, and G. Bersuker, “Electrical Observation of Deep Traps in High-k/Metal Gate Stack Transistors”, IEEE Electron Device Lett., 26, 839 (2005).
[3.9] W. Abadeer, and W. Ellis, “Behavior of NBTI under AC Dynamic Circuit Conductions”, Reliability Physics Symposium Proceedings, 17 (2003).
[3.10] Vijay Reddy, Anand T. Krishnan, Andrew Marshall, John Rodriguez, Sreedhar Natarajan, Tim Rost, and SrikanthKrishnan, “Impact of Negative Bias Temperature Instability on Digital Circuit Reliability,” Proceedings of the Inter. ReL Phys. Symp., pp. 248-254 (2002).
[3.11] R. Thewes, R. Brederlow, C. Schhmder, P. Wieezorek, B. Ankele, A. Hesener, J. Holz, S. Kessel, W. Weber, “Evaluation of MOSFET Reliability in Analog Application,” European Solid- State Device Research Conf. (2001).
[3.12] B. Zhu, J. S. Snehle, Y. Chen, and J. B. Bernstein, “Negative Bias Temperature Instability of Deep Sub- Micron p-MOSFETs Under Pulsed Bias Stress”, Proceedings of the Integrated Reliability Workshop (to be published) (2002).
[3.13] L. Pantisano, E. Cartier, A. Kerber, R. Degraeve, M. Lorenzini, M. Rosmeulen, G. Groeseneken, H.E. Maes, IMEC, Leuven, Belgium, “Dynamics of Threshold Voltage Instability in Stacked High-k Dielectrics: Role of the Interfacial Oxide”, Symp. VLSI Tech. Dig., pp.163 (2002).
[3.14] G. Bersuker, J. H. Sim, C. S. Park, C. D. Young, S. V. Nadkarni, R. Choi, and B. H. Lee, “Mechanism of Electron Trapping and Characteristics of Traps in HfO2 Gate Stacks” IEEE Trans. Device And Materials Reliability, 7, 138 (2007).
[3.15] J. L. Gavartin, A. L. Shluger, A. S. Foster, and G. I. Bersuker, “The role of nitrogen-related defects in high-k dielectric oxides: Density-functional studies,” J. Appl. Phys., 97, 053704 (2005).

Chapter4
[4.1] S.M.SZE, “Physics of Semiconductor Devices,” WILEY-INTERSCIENCE, Third Edition, Hoboken, New Jersey, 2007.
[4.2] M. L. Green, E. P. Gusev, R. Degraeve, and E. Garfunkel, “Ultrathin (<4 nm) SiO2 and Si-O-N Gate Dielectrics Layers for Silicon Microelectronics: Understanding the Processing, Structure and Physical and Electrical Limits,” J. Appl. Phys., 90, 2057 (2001).
[4.3] Y. Kim, G. Gebara, M. Freiler, J. Barnett, D. Riley, J. Chen, K. Torres, J. E. Lim, B. Foran, F. Shaapur, A. Agarwal, P. Lysaght, G. A. Brown, C. Young, S. Borthakur, H. J. Li, B. Nguyen, P. Zeitzoff, G. Bersuker, D. Derro, R. Bergmann, R. W. Murto, Alex Hou, H. R. Huff, E. Shero, C. Pomarede, M. Givens, M. Mazanec, and C. Werkhoven, “Conventional n-channel MOSFET device using single layer HfO2 and ZrO2 as high-k gate dielectrics with polysilicon gate electrode,” in IEDM Tech. Dig., pp. 455 (2001).
[4.4] Sufi Zafar, Alessandro Callegari, Evgeni Gusev and Massimo V. Fischetti, “Charge trapping in high-k gate dielectric stacks,” in IEDM Tech. Dig., pp. 517-520 (2002).
[4.5] Hyung-Suk Jung, Jeong Hwan Kim, Joohwi Lee, Sang Young Lee, Un Ki Kim, Cheol Seong Hwang, Jung-Min Park, Weon-Hong Kim, Min-Woo Song, and Nae-In Lee, “Bias Temperature Instability Characteristics of n- and p-Type Field Effect Transistors Using HfO2 Gate Dielectrics and Metal Gate”, J. Electrochem. Soc., 157, H355 (2010)
[4.6] B. Zhu, J. S. Snehle, Y. Chen, and J. B. Bernstein, “Negative Bias Temperature Instability of Deep Sub- Micron p-MOSFETs Under Pulsed Bias Stress”, Proceedings of the Integrated Reliability Workshop (to be published) (2002).
[4.7] R. Chau, S. Datta, M. Doczy, B. Doely, J. Kavalieros and M. Metz, “High-k/metal-gate stack and its MOSFET characteristics,” IEEE Electron Device Lett., vol. 25, pp. 408-410 (2004).
[4.8] G. Groeseneken, H.E. Maes, N. Beltran, R.F. De Keersmaecker, “A reliable approach to charge-pumping measurements in MOS transistors”, IEEE Trans. Electron devices, Vol. 31, pp. 42 (1984).
[4.9] C. S. Lu, H. C. Lin and Y. J. Lee, “Improvement of negative-bias-temperature instability in SiN-capped p-channel MOSFETs using ultrathin HfO2 buffer layer,” J. Electrochem. Soc., vol. 154, pp. H1036-H1040, (2007).
[4.10] J. S. Brugler and P. G. A. Jespers, “Charge pumping in MOS devices,” IEEE Trans. Electron Dev. ED-16, pp. 297-302 (1969).
[4.11] P. Heremans, J. Witters, G. Groeseneken, H.E. Maes, “Analysis of the charge pumping technique and its application for the evaluation of MOSFET degradation”, IEEE Trans. Electron devices, Vol. 36, pp. 1318 (1989).

Chapter5
[5.1] M. L. Green, E. P. Gusev, R. Degraeve, and E. Garfunkel, “Ultrathin (<4 nm) SiO2 and Si-O-N Gate Dielectrics Layers for Silicon Microelectronics: Understanding the Processing, Structure and Physical and Electrical Limits,” J. Appl. Phys., 90, 2057 (2001).
[5.2] Y. Kim, G. Gebara, M. Freiler, J. Barnett, D. Riley, J. Chen, K. Torres, J. E. Lim, B. Foran, F. Shaapur, A. Agarwal, P. Lysaght, G. A. Brown, C. Young, S. Borthakur, H. J. Li, B. Nguyen, P. Zeitzoff, G. Bersuker, D. Derro, R. Bergmann, R. W. Murto, Alex Hou, H. R. Huff, E. Shero, C. Pomarede, M. Givens, M. Mazanec, and C. Werkhoven, “Conventional n-channel MOSFET devices using single layer HfO2 and ZrO2 as high-k gate dielectrics with polysilicon gate electrode”, in IEDM Tech. Dig., pp. 455 (2001).
[5.3] G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C. Parthasarathy, E. Vincent, and G. Ghibaudo, “Review on High-k Dielectrics Reliability Issues”, IEEE Trans. Device And Materials Reliability, 5, 5(2005).
[5.4] M. Casse, L. Thevenod, B. Guillaumot, L. Tosti, F. Martin, J. Mitard, O. Weber, F. Andrieu, T. Ernst, G. Reimbold, T. Billon, M. Mouis, and F. Boulanger, “Carrier Transport in HfO2/Metal Gate MOSFETs: Physical Insight Into Critical Parameters”, IEEE Trans. Electron Devices, 53, 759 (2006).
[5.5] S. Zafar, A. Kumar, E. Gusev, and E. Cartier, “Threshold Voltage Instabilities in High-k Gate Dielectric Stacks”, IEEE Trans. Device Mater. Rel., 5, 45 (2005).
[5.6] J. C. Liao, Yean-Kuen Fang, Y. T. Hou, W. H. Tseng, P. F. Hsu, K. C. Lin, K. T. Huang, T. L. Lee, and M. S. Liang, “Investigation of Bulk Traps Enhanced Gate-Induced Leakage Current in Hf-Based MOSFETs”, IEEE Trans. Electron Device Letters, 29, 509 (2008).
[5.7] E. Amat, T. Kauerauf, R. Degraeve, A. Dee Keersgieter, R. Rodr&#237;guez, M. Nafr&#237;a, X. Aymerich, and G. Groeseneken, “Channel Hot-Carrier degradation under static stress in short channel transistors with high-k/metal gate stacks”, in Proc. 9th Int. Conf. Ultimate Integr. Silicon, pp.103 (2008).
[5.8] S. Cimino, L. Pantisano, M. Aoulaiche, R. Degraeve, D. H. Kwak, F. Crupi, G. Groeseneken, and A. Paccagnella, “Hot Carrier Degradation n-Channel HfSiON MOSFETS: Electron the Device Performance and Lifetime”, in Proc. IEEE Int. Rel. Phys. Symp., pp.275 (2005).
[5.9] M. Takayanagi, T. Watanabe, R. Iijima, K. Ishimaru, and Y. Tsunashima, “Investigation of Hot Carrier Effects in n-MISFETs with HfSiON Gate Dielectric” , in Proc. IEEE Int. Rel. Phys. Symp., pp.13 (2004).
[5.10] I. Crupi, “Hot carrier effects in n-MOSFETs with SiO2/HfO2/HfSiO gate stack and TaN metal gate”, Microelectronic Engineering, 86, 1 (2009).
[5.11] Esteve Amat, Thomas Kauerauf, Robin Degraeve, Rosana Rodr&#237;guez, Montserrat Nafr&#237;a, Xavier Aymerich, and Guido Groeseneken, “Gate Voltage Influence on the Channel Hot-Carrier Degradation of High-k-Based Devices”, IEEE transactions on device and materials reliability, 11, 1530 (2011).
[5.12] X. H. Ma, Y. R. Cao, H. X. Gao, H. F. Chen, and Y. Hao, “Behaviors of gate induced drain leakage stress in lightly doped drain n-channel metal-oxide-semiconductor field-effect transistors,” Appl. Phys. Lett., 95, 152107 (2009).
[5.13] J. L. Gavartin, A. L. Shluger, A. S. Foster, and G. I. Bersuker, “The role of nitrogen-related defects in high-k dielectric oxides: Density-functional studies”, J. Appl. Phys., 97, 053704 (2005).

Chapter6
[6.1] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “High-κ gate dielectrics: Current status and materials properties considerations,” J. Appl. Phys., 89, 5243 (2001).
[6.2] G. Ribes, J. Mitard, M. Denais, S. Bruyere, F. Monsieur, C. Parthasarathy, E. Vincent, and G. Ghibaudo, “Review on High-k Dielectrics Reliability Issues”, IEEE Trans. Device And Materials Reliability, 5, 5(2005).
[6.3] W. Abadeer, and W. Ellis, “Behavior of NBTI under AC Dynamic Circuit Conductions”, Reliability Physics Symposium Proceedings, 17 (2003).
[6.4] Vijay Reddy, Anand T. Krishnan, Andrew Marshall, John Rodriguez, Sreedhar Natarajan, Tim Rost, and SrikanthKrishnan, “Impact of Negative Bias Temperature Instability on Digital Circuit Reliability,” Proceedings of the Inter. ReL Phys. Symp., pp. 248-254 (2002).
[6.5] Dieter K. Schroder, and Jeff A. Babcock, “Negative bias temperature instability: Road to cross in deep submicron silicon semiconductor manufacturing,” J. Appl. Phys., vol. 94, pp. 1-18 (2003).
[6.6] C. S. Lu, H. C. Lin and Y. J. Lee, “Improvement of negative-bias-temperature instability in SiN-capped p-channel MOSFETs using ultrathin HfO2 buffer layer,” J. Electrochem. Soc., vol. 154, pp. H1036-H1040, (2007).
[6.7] H. R. Rhee, H. Lee, T. Ueno, D. S. Shin, S. H. Lee, Y. Kim, A. Samoilov, P. O. Hansson, M. Kim, H. S. Kim, and N. I. Lee, “Negative Bias Temperature Instability of Carrier-Transport Enhanced pMOSFET with Performance Boosters,” in IEDM Tech. Dig., pp. 692-695 (2005).
[6.8] B. Zhu, J. S. Snehle, Y. Chen, and J. B. Bernstein, “Negative Bias Temperature Instability of Deep Sub- Micron p-MOSFETs Under Pulsed Bias Stress”, Proceedings of the Integrated Reliability Workshop (to be published) (2002).
[6.9] L. Pantisano, E. Cartier, A. Kerber, R. Degraeve, M. Lorenzini, M. Rosmeulen, G. Groeseneken, H.E. Maes, IMEC, Leuven, Belgium, “Dynamics of Threshold Voltage Instability in Stacked High-k Dielectrics: Role of the Interfacial Oxide”, Symp. VLSI Tech. Dig., pp.163 (2002).
[6.10] M. Casse, L. Thevenod, B. Guillaumot, L. Tosti, F. Martin, J. Mitard, O. Weber, F. Andrieu, T. Ernst, G. Reimbold, T. Billon, M. Mouis, and F. Boulanger, “Carrier Transport in HfO2/Metal Gate MOSFETs: Physical Insight Into Critical Parameters”, IEEE Trans. Electron Devices, 53, 759 (2006).
[6.11] Yuichiro Mitani, Makoto Nagamine, Hideki Satake, and Akira Toriuni, “ NBTI Mechanism in Ultra-thin Gate Dielectric-Nitrogen-Originated Mechanism in SiON”, IEDM, pp.509-512,(2002).