論文使用權限 Thesis access permission:校內校外均不公開 not available
開放時間 Available:
校內 Campus:永不公開 not available
校外 Off-campus:永不公開 not available
論文名稱 Title |
應用低誤差倍乘型式數位類比轉換器實現3.3伏特十位元50MHz取樣頻率之管線式類比數位轉換器 A 3.3V 10-bit 50-MS/s Pipelined Analog-to-Digital Converter with Low-Deviation MDAC |
||
系所名稱 Department |
|||
畢業學年期 Year, semester |
語文別 Language |
||
學位類別 Degree |
頁數 Number of pages |
63 |
|
研究生 Author |
|||
指導教授 Advisor |
|||
召集委員 Convenor |
|||
口試委員 Advisory Committee |
|||
口試日期 Date of Exam |
2004-06-30 |
繳交日期 Date of Submission |
2004-07-14 |
關鍵字 Keywords |
類比數位轉換器、管線式 ADC, pipelined |
||
統計 Statistics |
本論文已被瀏覽 5667 次,被下載 0 次 The thesis/dissertation has been browsed 5667 times, has been downloaded 0 times. |
中文摘要 |
本篇論文提出一個可操作在解析度十位元且取樣頻率為50MHz 之管線式類比數位轉換器(10bit 50MSample/sec Pipelined Analog-to-Digital Converter)。我們提出四位元低偏移誤差倍乘式數位類比轉換器(Low-Deviation Multiplying Digital-to-Analog Converter)來取代傳統型式的倍乘式數位類比轉換器,使用非固定型式的回授電容設計,在原理上比傳統型式固定回授電容最後實際輸出範圍還要更接近於理想值,使得其線性度將會比傳統的倍乘式數位類比轉換器還要好。將其運用在十位元的管線式類比數位轉換器中,微分非線性誤差為±0.31 LSB,積分非線性誤差為±0.57 LSB,而使用傳統型式構成的10位元的管線式類比數位轉換器,微分非線性誤差為±0.5 LSB,積分非線性誤差為±1.17 LSB。 本篇論文所設計之類比數位轉換器採用台灣積體電路製造公司(TSMC) 0.35µm 2P4M CMOS 製程來實現,且供應電壓為3.3V於取樣速度50MHz 下,類比數位轉換的操作電壓範圍為0.5至2.5V,而功率消耗為64mW。 |
Abstract |
A 10-bit 50MSample/sec pipelined analog-to-digital converter is described in this thesis. We replaced conventional multiplying digital-to-analog converter with low-deviation multiplying digital-to-analog converter in the proposed pipelined analog-to-digital converter. Using nonregular feedback capacitors achieves better linearity than using conventional regular feedback capacitors in the multiplying digital-to-analog converter. The accuracy of this pipelined analog-to-digital converter can be also improved, the result shows that the DNL is ±0.31 LSB, INL is about ±0.57LSB. Our proposed pipelined analog-to-digital converter is designed by TSMC 2P4M 0.35um process. It operates at 3.3V power supply voltage with 0.5 to 2.5V reference voltage, and the power consumption is about 64mW. |
目次 Table of Contents |
第一章、導論.........................................1 第二章、管線式類比數位轉換器的架構與問題考量...........7 2-1、架構與運作………………………………………………………7 2-2、設計時所須注意的問題…………………………………………8 第三章、運用於管線式類比數位轉換器中的次級電路….15 3-1、雙取樣的取樣保持電路………………………………………..15 3-2、應用增益提高技術的運算放大器……………………………..19 3-3、四位元快閃式類比數位轉換器………………………………..23 3-4、比較器電路……………………………………………………..26 3-5、低誤差倍乘式數位類比轉換器………………………………..28 第四章、模擬結果…………………………………………..37 第五章、結論與未來的研究方向…………………………..43 5-1、結論……………………………………………………………..43 5-2、未來研究方向…………………………………………………..44 參考文獻……………………………………………………..45 附錄A………………………………………………………..48 附錄B………………………………………………………..52 |
參考文獻 References |
[1] C.-W. Hsu, T.-H. Kuo, “6-b 500MHz flash A/D converter with new design techniques,” IEE Proc.-Circuits Devices Syst, vol. 150, No. 5, October 2003. [2] B. Razavi, B. A. Wooley, “A 12-b 5-Msample/s two-step CMOS A/D converter,” IEEE Journal of Solid-State Circuits, vol. 27, No. 12, pp. 1667 –1678, Dec. 1992. [3] B. P. Brandt, J. Lutsky, “A 75-mW, 10-b, 20-MSPS CMOS Subranging ADC with 9.5 Effective Bits at Nyquist,” IEEE Journal of Solid-State Circuits, vol. 34, No. 12, pp. 1788 –1795, Dec. 1999. [4] K. Hadidi, V. S. Tso, G. C. Temes, “An 8-b 1.3-MHz successive-approximation A/D converter,” IEEE Journal of Solid-State Circuits, vol. 25, No. 3, pp. 880 –885, Jun 1990. [5] A. M. Abo, P. R. Gray “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE Journal of Solid-State Circuits, vol. 34, No. 5, pp. 599 –606, May 1999. [6] J. D. Maeyer, P. Rombouts, L. Weyten, “A Double-sampling Extended-Counting ADC,” IEEE Journal of Solid-State Circuits, vol. 39, No. 3, pp. 411–418, March. 2004. [7] J. C. Lin, V. K. Semenov, K. K. Likharev, “Design of SFQ-Counting Analog-to-Digital Converter,” IEEE Transactions on Applied Superconductivity, vol. 5, No. 2, June. 1995. [8] G. Burra, K. S. Chao, “A high-speed high-resolution oversampled A/D converter,” IEEE International Symposium on Circuits and Systems, vol. 2, No. 1, pp. 1282 –1285, May 1993. [9] M. Inerfield, W. Skones, S. Nelson, D. Ching, P. Cheng, C. Wong, “High Dynamic Range InP HBT Delta-Sigma Analog-to-Digital Converters,” IEEE Journal of Solid-State Circuits, vol. 38, No. 9, pp. 1524–1532, September. 2003. [10] S. Mukherjee, C. Srinivasan, V. Pawar, S. Mathur, K. Godbole, “A 2.5 V 10 bit SAR ADC,” VLSI Design, vol. 1, No. 4, pp. 525 –526, Jan 1997. [11] F. L. Keng, C. A. T. Salama, “Low-power current-mode algorithmic ADC,” IEEE International Symposium on Circuits and Systems, vol. 5, No. 1, pp. 473 –476, June 1994. [12] O. E. Erdogan, “A CMOS Ratio-Independent and Gain-Insensitive Algorithmic Analog-to-Digital Converter,” IEEE Journal of Solid-State Circuits, vol. 32, No. 6, pp. 920, March. 1997. [13] G. Giustolisi, G. Palumbo, S. Pennisi, “Resolution of a Current-Mode Algorithmic Analog-to-Digital Converter,” IEEE Trans. Circuits Syst I, vol. 49, pp. 1480-1486, October. 2002. [14] Y. Yoshii, K. Asano, M. Nakamura, C. Yamada, “An 8 bit, 100 ms/s flash ADC,” IEEE Journal of Solid-State Circuits, vol. 19, No. 6, pp. 842 –846, Dec 1984. [15] K. Uyttenhove, M. S. J. Steyaert, “A 1.8-V 6-Bit 1.3-GHz Flash ADC in 0.25-um CMOS,” IEEE Journal of Solid-State Circuits, vol. 38, No. 7, pp. 1115-1122, JULY 2003. [16] H. van der Ploeg, R. Remmers, “A 3.3-V, 10-b, 25-MSample/s Two-Step ADC in 0.35-um CMOS, “IEEE Journal of Solid-State Circuits, vol. 34, No. 12, pp. 1803-1811, December 1999. [17] M. P. Flynn, B. Sheahan, “A 400-Msample/s, 6-b CMOS folding and interpolating ADC,” IEEE Journal of Solid-State Circuits, vol. 33, No. 2, pp. 1932 –1938, Dec. 1998. [18] M. –H. Liu, S. –I. Liu, “An 8-bit 10MS/s Folding and Interpolating ADC Using the Continuous-Time Auto-Zero Technique,” IEEE Journal of Solid-State Circuits, vol. 36, No. 1, pp. 122-128, January 2001. [19] H. C. Choi, H. J. Park, S. K. Bae, J. W. Kim, P. Chung, “A 1.4 V 10-bit 20 MSPS pipelined A/D converter,” IEEE International Symposium on Circuits and Systems, vol. 1, No. 1, pp. 439 –442, May 2000. [20] J. Li, U. –K. Moon,” Background Calibration Techniques for Multistage Pipelined ADCs With Digital Redundancy,” IEEE Trans. Circuits Syst II, vol. 50, pp. 531-538, SEPTEMBER. 2003. [21] D. Miyazaki, S. Kawahito, M. Furuta, “A 10-b 30-MS/s Low-Power Pipelined CMOS A/D Converter Using a Pseudodifferential Architecture,” IEEE J. Solid-State Circuits, vol. 38, NO. 2, Feb. 2003. [22] S. –M. Yoo, T. –H. Oh, “A 2.5V 10b 120 MSample/s CMOS Pipelined ADC with high SFDR,” IEEE Custom Integrated Circuits Conf. pp. 441-444, 2002 [23] S. –Y. Chuang, T. L. Sculley,”A Digitally Self-Calibrating 14-bit 10-MHz CMOS Pipelined A/S Converter,” IEEE J. Solid-State Circuits, vol. 37, pp. 674-683, JUNE. 2002. [24] J. H. Shieh, P. Mahesh, B. J. Sheu, “Measurement and Analysis of Charge Injection in MOS Analog Switches”, IEEE Journal of Solid State Circuit, vol. 22, No. 2, pp. 277-281, April 1987. [25] S. Mathur, M. Das, P. Tadeparthy, S. Ray, S. Mukherjee, Dinakaran B. L.”A 115mW 12-Bit 50MSPS Pipelined ADC,” IEEE Conf, pp. 913-916, 2002. [26] L. Sumanen, M. Waltari, T. Korhonen, K. Halonen,”A Digital Self-Calibration Method For Pipeline A/D Converters,”IEEE Conf, pp. 792-795, 2002. [27] M. Waltari, K. Halonen, “Timing skew insensitive switching for double sampled circuits,” IEEE International Symposium on Circuits and Systems, vol. 2, No. 2, pp. 61-64, Jul. 1999. [28] L. Dai, R. Harjani, “ CMOS switched-op-amp-based sample-and-hold circuit,” IEEE Journal of Solid-State Circuits, vol. 35, No. 1, pp. 109 –113, Jan 2000. [29] S. Brigati, F. Maloberti, G. Torelli, “A CMOS sample and hold for high-speed ADC’s,” IEEE International Symposium on Circuits and Systems, vol. 1, No. 1, pp. 163 –166, May 1996. [30] H. Liu, Xiaohong, M. Hassoun, “Components of a 12-bit 50Ms/s Non-radix 2 Pipeline Analog-to-Digital Converter,” IEEE Midwest Symp, on Circuits and Systems, Lansing MI, pp. 400-403, Aug 2000. [31] K. Bult, G. J. G.. M. Geelen, “A Fast-Settling CMOS Op Amp for SC Circuits with 90-dB DC Gain,” IEEE Journal of Solid-State Circuits, vol. 25, No. 6, pp. 1379 –1384, Dec 1990. [32] H. Liu and M. Hassoum, “A 9-b 40MSample/s Reconfigurable Pipeline Analog-to-Digital Converter,” IEEE Trans. Circuits Syst II, vol.49 pp. 449-456, July. 2002. [33] M. Choi, A. A. Abidi, “A 6-b 1.3-Gsample/s A/D Converter in 0.35-um CMOS,” IEEE Journal of Solid-State Circuits, vol. 36, No. 12, pp. 1847 –1858, Dec 2001. [34] Y. –M. Lin, B. Kim, P. R. Gray, “A 13 bit 2.5MHz Self-Calibrated Pipelined A/D Converter in 3um CMOS,” IEEE Journal of Solid-State Circuits, vol. 36, No. 26, pp. 628 –636, April 1991. [35] G. –C. Ahn, H. –C. Choi, S. –I. Lim, S. –H. Lee, C. –D. Lee, ”A 12-b 10-MHz 250-mW CMOS A/D Converter,” IEEE J. Solide-State Circuits, vol. 31, pp. 2030-2035, Dec 1996. [36] M. Yostsuyanagi, T. Etoh, K. Hirata, “A 10-b 50-MHz Pipelined CMOS A/D Converter with S/H,” IEEE J. Solide-State Circuits, vol. 28 NO.3, , pp. 292-300, MARCH 1993. [37] D. –Y. Chang, U. –K. Moon, “A 1.4-V 10-bit 25-MS/s Pipelined ADC Using Opamp-Reset Switching Technique,” IEEE J. Solide-State Circuits, vol. 38, NO, 8, pp. 1401-1404, AUGUST 2003. [38] S. M. Jamal, D. Fu, N. C. –J Chang, S. H. Lewis, “A 10-b 120-Msample/s Time-Interleaved Analog-to-Digital Converter With Digital Background Calibration,” IEEE J. Solide-State Circuits, vol. 37, pp. 1618-1626, Dec 2002. [39] A. Shabra, H. –S. Lee, “A 12-bit Mismatch-Shaped Pipelined A/D Converter,” Symposlum on VLSI Circuits Digest of Technical Papers, 2001. |
電子全文 Fulltext |
本電子全文僅授權使用者為學術研究之目的,進行個人非營利性質之檢索、閱讀、列印。請遵守中華民國著作權法之相關規定,切勿任意重製、散佈、改作、轉貼、播送,以免觸法。 論文使用權限 Thesis access permission:校內校外均不公開 not available 開放時間 Available: 校內 Campus:永不公開 not available 校外 Off-campus:永不公開 not available 您的 IP(校外) 位址是 3.88.16.192 論文開放下載的時間是 校外不公開 Your IP address is 3.88.16.192 This thesis will be available to you on Indicate off-campus access is not available. |
紙本論文 Printed copies |
紙本論文的公開資訊在102學年度以後相對較為完整。如果需要查詢101學年度以前的紙本論文公開資訊,請聯繫圖資處紙本論文服務櫃台。如有不便之處敬請見諒。 開放時間 available 已公開 available |
QR Code |