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博碩士論文 etd-0714104-174845 詳細資訊
Title page for etd-0714104-174845
論文名稱
Title
應用低誤差倍乘型式數位類比轉換器實現3.3伏特十位元50MHz取樣頻率之管線式類比數位轉換器
A 3.3V 10-bit 50-MS/s Pipelined Analog-to-Digital Converter with Low-Deviation MDAC
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
63
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2004-06-30
繳交日期
Date of Submission
2004-07-14
關鍵字
Keywords
類比數位轉換器、管線式
ADC, pipelined
統計
Statistics
本論文已被瀏覽 5667 次,被下載 0
The thesis/dissertation has been browsed 5667 times, has been downloaded 0 times.
中文摘要
本篇論文提出一個可操作在解析度十位元且取樣頻率為50MHz 之管線式類比數位轉換器(10bit 50MSample/sec Pipelined Analog-to-Digital Converter)。我們提出四位元低偏移誤差倍乘式數位類比轉換器(Low-Deviation Multiplying Digital-to-Analog Converter)來取代傳統型式的倍乘式數位類比轉換器,使用非固定型式的回授電容設計,在原理上比傳統型式固定回授電容最後實際輸出範圍還要更接近於理想值,使得其線性度將會比傳統的倍乘式數位類比轉換器還要好。將其運用在十位元的管線式類比數位轉換器中,微分非線性誤差為±0.31 LSB,積分非線性誤差為±0.57 LSB,而使用傳統型式構成的10位元的管線式類比數位轉換器,微分非線性誤差為±0.5 LSB,積分非線性誤差為±1.17 LSB。

本篇論文所設計之類比數位轉換器採用台灣積體電路製造公司(TSMC) 0.35µm 2P4M CMOS 製程來實現,且供應電壓為3.3V於取樣速度50MHz 下,類比數位轉換的操作電壓範圍為0.5至2.5V,而功率消耗為64mW。
Abstract
A 10-bit 50MSample/sec pipelined analog-to-digital converter is described in this thesis. We replaced conventional multiplying digital-to-analog converter with low-deviation multiplying digital-to-analog converter in the proposed pipelined analog-to-digital converter. Using nonregular feedback capacitors achieves better linearity than using conventional regular feedback capacitors in the multiplying digital-to-analog converter. The accuracy of this pipelined analog-to-digital converter can be also improved, the result shows that the DNL is ±0.31 LSB, INL is about ±0.57LSB.

Our proposed pipelined analog-to-digital converter is designed by TSMC 2P4M 0.35um process. It operates at 3.3V power supply voltage with 0.5 to 2.5V reference voltage, and the power consumption is about 64mW.
目次 Table of Contents
第一章、導論.........................................1
第二章、管線式類比數位轉換器的架構與問題考量...........7
2-1、架構與運作………………………………………………………7
2-2、設計時所須注意的問題…………………………………………8
第三章、運用於管線式類比數位轉換器中的次級電路….15
3-1、雙取樣的取樣保持電路………………………………………..15
3-2、應用增益提高技術的運算放大器……………………………..19
3-3、四位元快閃式類比數位轉換器………………………………..23
3-4、比較器電路……………………………………………………..26
3-5、低誤差倍乘式數位類比轉換器………………………………..28
第四章、模擬結果…………………………………………..37
第五章、結論與未來的研究方向…………………………..43
5-1、結論……………………………………………………………..43
5-2、未來研究方向…………………………………………………..44
參考文獻……………………………………………………..45
附錄A………………………………………………………..48
附錄B………………………………………………………..52
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