本篇論文提出一個可以操作2.5伏特供應電壓，解析度八位元且取樣頻率為100MHz之折疊內差型式類比數位轉換器(2.5V 8bit 100MSample/sec Folding and Interpolation Analog to Digital Converter)。首先我們採用疊接型式的折疊放大器來降低功率消耗。由於疊接型式的折疊放大器中的差動對是被疊接串聯起來，所以減少了差動對所需的參考電流源，因此大大的減少了功率消耗。為了更降低功率的消耗，我們把供應電壓降至2.5伏特，可是卻因此而使得折疊放大器在轉換訊號時，因為供應電壓的不足而無法正常的工作，造成輸出訊號有偏移的問題。因此我們提出在折疊電路後面加上後端放大器來減輕此問題。如此一來使得整體電路的功率消耗大大的降低至15.292mW。此外因為疊接差動對的寄生電容比傳統串接差動對的寄生電容小，再加上我們使用離散式折疊技巧，減少了每一個次折疊放大器的折疊因子，所以減輕了頻率增加效應(frequency multiplication effect)的問題，使得類比輸入訊號的頻寬增大。採用為了使電壓比較器的可用範圍可以達到較高電壓的比較訊號，我們使用N型的差動輸入端，因為N型的差動輸入級的可用範圍比P型的高。經過這些技巧的改良可以使得輸入訊號的頻寬和整體電路的功率消耗大大的改善。

本論文所設計的類比數位轉換器採用台灣積體電路製造公司(TSMC)0.35um
2P4M CMOS製程來實現，且供應電壓為2.5伏特。在取樣頻率為100MHz下，類比至數位轉換的操作電壓範圍為1伏特~2.4伏特，功率消耗為15.292mW，微分非線性誤差約為+/-0.55LSB，積分非線性誤差約為+1.7LSB ~ -0.8LSB。

A 2.5V 8-bit 100MSample/sec folding and interpolation analog to digital converter is described in this thesis. First, a cascoding folding amplifier is used for improve power consumption. The differential pairs of the folding amplifier are cascoded to reduce the numbers of reference current source, so the power consumption is reduced. In order to reduce more power consumption, we drop the power supply down to 2.5V. However, the power supply is not large enough to keep the folding amplifier working normally and it causes the output signal aberration. Hence, we propose a back-end amplifier to connect the folding amplifier to overcome the problem. Therefore, the power consumption of all circuit is reduced to 15.292mW. Moreover, the capacitive loading at the output of the cascoded differential pairs is smaller than that of conventional cascaded differential pairs, and we employ a distributed folding technique to reduce the folding factors of each folding amplifier. Therefore, we improve the frequency multiplication effect to increase the analog input signal bandwidth. Beside, in order to heave the input signal range of the voltage mode comparator, we employ an n-channel input stage. Because the input signal range of n-channel is higher than that of p-channel input stage. By using these techniques, the input signal bandwidth and the power consumption of overall circuit are improved greatly.
The proposed analog to digital converter is designed by TSMC 0.35μm 2P4M CMOS process, and it operates at 2.5V power supply voltage with 1V to 2.4V reference voltage. The simulation results show that the power consumption is 15.292mW, DNL is +/- 0.55LSB, and INL is 1.7LSB ~ -0.8LSB.

第一章 導論.............................................1
第二章 折疊內插型式類比數位轉換器的原理與架構說明.............................................13
第三章 整體電路的設計.................................19
3-1 折疊放大器.......................................19
3-2 內插器...........................................24
3-3 比較器...........................................28
3-3-1 電流比較器................................28
3-3-2 電壓比較器................................30
3-4 編碼器與解碼器...................................34
3-5 錯誤矯正電路.....................................36
第四章 模擬結果........................................38
第五章 結論與未來研究方向............................44
5-1 結論.............................................44
5-2 未來研究方向.....................................44
參考文獻...............................................45
附錄A、Layout圖........................................49
附錄B、發表的論文......................................53

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