本論文包含兩個主題，第一個主題是一種使用位移式拋物線內插方法之無唯讀記憶體直接數位頻率合成器；第二個主題是以矽基底整合光偵測器及轉阻放大器之光電積體電路元件。
在第一個研究主題中，無唯讀記憶體之直接數位頻率合成器使用一位移式拋物線內插方法，係將拋物線方程式加入一個初始相位值，亦即位移(offset)，使得可以改善輸出弦波的頻譜純度，並且加入管線化設計用以提升整體電路的工作時脈。
在第二個研究主題中，光電積體電路元件利用互補式金屬-氧化層-半導體(Complementary Metal-Oxide-Semiconductor, CMOS)製程製做出轉阻放大器，並且利用其矽基底，將以III-V族元素所製作的光偵器藉由應力(wafer bound)的方式以混合式積體電路(Hybrid Integrated Circuits)技術整合，藉以降低由異質接面所造成的頻寬的限制。

This thesis includes two topics. The first topic is a ROM-less DDFS (Direct Digital Frequency Synthesizer) using a parabolic polynomial in-terpolation method with an offset adjustment. The second one is the de-sign and fabrication of a silicon-based OEIC(optoelectronic integrated circuit) comprising photodetectors and transimpedance amplifiers.
The ROM-less DDFS employs a parabolic polynomial interpola?tion method with an offset adjustment, where an initial phase offset is added into parabolic polynomials. Besides, the pipelining architecture is adopted to improve the speed of the proposed DDFS.
The OEIC uses the hybrid integration technique to integrate the III-V optoelectronic devices (photodetector) and CMOS integrated circuits (transimpedance amplifier) onto the same substrate (silicon substrate) by the wafer bounding technique. With the realization of the hybrid in-tegration, the bandwidth degeneration resulted from the traditional wire bounding can be avoided.

致謝 i
摘要 ii
Abstract iii
目錄 iv
圖目錄 vi
表目錄 ix
第一章 概論 1
1.1 研究動機 1
1.1.1 無唯讀記憶體之直接數位頻率合成器 1
1.1.2 光電積體電路 2
1.2 相關技術與文獻探討 3
1.2.1 利用內插方法之無唯讀記憶體直接數位式頻率合成器 3
1.2.2 使用矽基底之光電整合元件 9
1.3 論文架構 11
第二章 使用位移式拋物線內插方法之無唯讀記憶體直接數位頻率合成器 13
2.1 簡介 13
2.2 電路架構 14
2.3 電路設計 15
2.3.1 相位累加器 16
2.3.2 相位頻率轉換器 18
2.3.3 實際電路規格訂定 22
2.3.4 預計規格 23
2.4 電路模擬與晶片量測 24
2.4.1 電路模擬結果 24
2.4.2 晶片實作與量測結果 27
2.5 晶片實作量測之討論 33
第三章 以矽基底整合光偵測器及轉阻放大器之光電積體電路 36
3.1 簡介 36
3.2 電路設計 39
3.2.1 轉阻放大器 39
3.2.2 光偵測器 42
3.2.3 整合佈局規劃 44
3.2.4 預計規格 46
3.3 電路模擬跟晶片量測 46
3.3.1 電路模擬結果 46
3.3.2 晶片實作與量測結果 53
3.4 晶片實作量測之討論 58
第四章 結論與成果 61
參考文獻 63

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