由於現今社會車輛安全交通事故頻繁，促使世界各國汽車大廠紛紛致力於汽車警示防撞雷達系統之研發，在短時間內，讓駕駛人提早反應及預防交通事故發生，然而在汽車防撞雷達之接收機中，低雜訊放大器需具備高穩定性且將訊號放大之功用，確保接收之訊號得以最佳狀態呈現訊息，達到在短時間內提醒駕駛人避免交通事故發生。為了達到上述電路特性，傳統之低雜訊放大器(Low Noise Amplifier, LNA)需消耗較大功率以實現高增益及穩定度之特性；因此，本論文運用TSMC 0.18 μm CMOS製程開發一種同時兼具高增益與低功耗特性之低雜訊放大器設計，並應用於汽車防撞雷達相關產品。
本論文主要利用雙組態架構以簡化電路之複雜性，在不犧牲消耗功率之前提下，為了有效提高該元件之增益及穩定度，整個電路架構包含一個具gm-boosted之負電阻架構，具引入零級點觀念，具電阻與電容並聯技術，具源極隨耦器架構之緩衝級電路，以及具低雜訊共源極隨偶器做為輸入匹配。
本論文所開發之低雜訊放大器其操作頻率為24 GHz，符合汽車防撞雷達應用之頻率範圍(22-29 GHz)，晶片尺寸為1.4 mm × 0.7 mm。經由電磁模擬分析下，該低雜訊放大器增益(Gain)高達21.2 dB，該放大器電路之輸入反射損耗(Input Return Loss, IRL)為-18.1 dB以及輸出反射損耗(Output Return Loss, ORL)非常低，僅僅只有-28.1 dB；同時具備高隔離度(Reverse Isoation)之表現，僅僅只有-65.6 dB。最後，本論文所開發之晶片在1.5 V之操作偏壓下，其DC消耗功率相當低，僅僅只有 15.8 mW。

Due to the increasing percentages of traffic accidents in our society, many automobile manufacturers devote to develop various automotive anti-collision radar warning systems. Utilizing these radar warning systems, drivers can make some responses for preventing accident occurring within few seconds. However, for the automotive collision avoidance radar receivers, low-noise amplifiers must have the abilities of highly stable and amplify the signal to ensure the messages are shown perfectly and accurately, which give motorists attentions of traffic accident. To achieve the above characteristics, the traditional low-noise amplifiers consume greater power to meet the high-gain and stable functions. Therefore, this thesis employs the TSMC 0.18 μm CMOS process to develop low-noise amplifiers designs with both high gain and low power consumption which can be implemented in automotive anti-collision radars.
This thesis utilizes dual stage to simplify complexity of the circuit without sacrificing the power consumption. In order to effectively increase the gain and stability, the proposed low-noise amplifiers comprises a negative resistance of a gm-boosted technology, the concept of zero-pole point, the paralleled RC structure, a source follower buffer and a source-degeneration structure employed into the input stage improving input matching.
The proposed low noise amplifier with 1.4 mm × 0.7 mm chip size and its 24 GHz operating frequency is well suited for automotive radar (22-29 GHz) application. This low noise amplifier shows a very high-gain of 21.2 dB. Moreover, the amplifier presemts input return loss of -18.1 dB, very good output return loss of -28.1 dB and excellent isolation of -65.6 dB. Finally, a moderate consuming power are 15.8 mW of low noise amplifier from 1.5 V supply voltage.

論文審定書............................................................................................ i
摘要......................................................................................................iii
Abstract.................................................................................................iv
誌謝.....................................................................................................vi
目錄.....................................................................................................vii
圖目錄..................................................................................................ix
表目錄................................................................................................. xi
第一章 緒論 .........................................................................................1
1.1 研究背景.........................................................................................1
1.1.1 汽車防撞雷達之簡介......................................................................1
1.1.2 超外差式接收機架構之概述.............................................................2
1.1.3 傳統低雜訊放大器之簡介................................................................4
1.2 研究動機.........................................................................................6
1.3 論文架構.........................................................................................7
第二章 低雜訊放大器之原理概述.............................................................8
2.1 低雜訊放大器之重要性能參數............................................................8
2.1.1 散射參數.......................................................................................8
2.1.2 功率增益.....................................................................................10
2.1.3 穩定度.........................................................................................12
2.1.4 雜訊分析......................................................................................13
2.1.5 線性度.........................................................................................16
2.2 典型低雜訊放大器之單端與雙端電路架構............................................18
2.2.1 低雜訊放大器之單端疊接架構.........................................................18
2.2.2 低雜訊放大器之差動架構................................................................19
第三章 低雜訊放大器之設計.....................................................................20
3.1 本論文第一代與第二代低雜訊放大器之設計與模擬................................20
3.2本論文第三代低雜訊放大器之設計與模擬 .............................................25
3.3 設計規格表........................................................................................39
3.4 設計流程...........................................................................................39
第四章 結果與討論...................................................................................41
4.1 電路佈局設計.....................................................................................41
4.2 電路特性模擬.....................................................................................42
4.2.1 本論文第三代佈局前後電路之模擬與討論...........................................42
4.2.2 本論文與國內外研發成果之比較........................................................49
第五章 結論與未來展望............................................................................51
5.1 結論..................................................................................................51
5.2 未來展望...........................................................................................53
參考文獻.................................................................................................54

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