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博碩士論文 etd-0714117-175049 詳細資訊
Title page for etd-0714117-175049
論文名稱
Title
電荷陷阱對多晶矽穿隧式電晶體的閘極對汲極非交疊式結構影響之研究
Investigation of Impacts of Trap States on Poly-Si Tunnel Transistor With Gate-to-Drain Underlapping Structures
系所名稱
Department
畢業學年期
Year, semester
語文別
Language
學位類別
Degree
頁數
Number of pages
58
研究生
Author
指導教授
Advisor
召集委員
Convenor
口試委員
Advisory Committee
口試日期
Date of Exam
2017-07-24
繳交日期
Date of Submission
2017-08-14
關鍵字
Keywords
薄膜電晶體、穿隧式電晶體、非交疊效應、氨氣表面電漿處理
Underlap, NH3 Surface Plasma Treatment, TFET, TFT
統計
Statistics
本論文已被瀏覽 5687 次,被下載 718
The thesis/dissertation has been browsed 5687 times, has been downloaded 718 times.
中文摘要
本次實驗分兩大部分,分別探討閘極與汲極的非交疊、進行電漿處理之電特性與變溫效應分析,藉由電特性圖與能帶圖,清楚解釋電性現象。
穿隧式電晶體在閘極對汲極之非交疊時,等於在閘極與汲極之間多了一段本質區;在元件開啟狀態時,使電流從源極流向汲極,但因電流受到陷阱的影響,而增加路徑,造成載子遷移率的下降,最終使電流下降。在升溫後,陷阱的效應應該要減少,讓電流提升,但從電性圖上來看卻衰退的更加嚴重,證明電流與非交疊的長度強相關,從此判斷,穿隧電流在非交疊發生複合,使電流下降;而在較大非交疊的量時,穿隧載子全被複合無法到達汲極,最後只剩下本質空乏區中的產生電流。
由於多晶矽通道裡的晶粒邊界有著許多的缺陷,缺陷內含有許多懸浮鍵與應力鍵,使元件特性下降,包含次臨界擺幅變緩、開啟電流減少、漏電流上升、閘極電壓變大…等等。本次提出氨氣電漿處理鈍化晶粒邊界中的陷阱,藉著降低晶粒邊界陷阱能態與表面陷阱能態改善穿隧式電晶體下之非交疊電性。經過電漿處理後之元件,無論在升溫或室溫,皆有大幅的改善。
經過一系列的結果分析,可觀察到非交疊之結構與經電漿處理之穿隧式電晶體,在各方面展現出色的特性。
Abstract
This experiment will be divided into two parts. In the first part, we discuss the underlaps between gate and drain. The second part, we analyze the electrical characteristics and temperature change effect of NH3 plasma treatment. By analyzing electrical characteristics diagram and energy band diagram, we may clearly explain its electrical phenomena.
When there is underlap between gate and drain in tunneling field effect transistor, it is equivalent to adding an extra intrinsic Si region between gate and drain. As the device is in the on-state, electrons flow from the source to the drain. Electrons will encounter barrier height which cause by traps, leading to the degradation of carrier mobility that result in the degradation of driving current. As the temperature rise, electrons should have more energy to cross the barrier that lead to higher mobility and higher driving current. However, from the perspective of electrical characteristics diagram, the driving current degradation is getting more serious as the temperature rise, suggesting that driving current degradation is dominant by the length of Underlap. On the basis of this, we may infer that the carriers has experienced a recombination process in the underlap region making the current degrade. As the underlap length is longer, the carrier has been fully recombined in the underlap region that no carrier can reach to the drain. Therefore, there is only generation current left in the empty intrinsic region leading to lower driving current.
Due to the various grain boundary defects of Poly-Si channel, consisting of many dangling bonds and strain bonds. These defects do harm to the device electrical characteristics including Subthreshold Swing degradation, On-State Current degradation and the increase of Threshold Voltage…and so on. In this study, ammonia plasma treatment is used to passivate grain boundary trap state and interface state. Devices after Plasma Treatment have significant improvements in both at rising temperature and room temperature.
After a series of analysis, we observe the Underlap structure and Plasma Treatments can help Tunnel Field Effect Transistor to show its outstanding characteristics from all perspectives.
目次 Table of Contents
論文審定書 i
致謝 ii
摘要 iii
Abstract iv
目錄 vi
圖目錄 viii
表目錄 xi
第一章 緒論 1
1.1 研究動機 1
1.1.1 薄膜電晶體(Thin Film Transistor, TFT) 2
1.2 晶粒之介紹 3
1.2.1 非晶矽(Amorphous) 3
1.2.2 單晶矽(Single Crystal, SC) 3
1.2.3 多晶矽(Polycrystalline) 3
1.2.4 晶粒邊界(Grain Boundary) 3
1.2.5 表面電漿處理(Surface Plasma Treatment) 4
1.2.6 短通道效應(Short Channel Effect, SCE) 5
1.3 穿隧式場效電晶體(Tunnel Field Effect Transistor, TFET) 6
1.3.1 能帶間穿隧(Band To Band Tunneling, BTBT) 6
1.3.2 陷阱輔助穿隧(Trap-Assisted Tunneling, TAT) 7
1.3.3 Shockley-Read-Hall 產生與複合 7
第二章 實驗步驟 16
2.1 元件製作 16
2.2 電性參數萃取與量測方式 17
2.2.1 量測方式及參數定義 17
2.2.2 交疊之長度 17
2.2.3 臨界電壓(Threshold Voltage, VT) 18
2.2.4 次臨界擺幅(Subthreshold Swing, S.S.) 18
2.2.5 晶粒邊界陷阱能態(Grain Boundary Trap State, NGB) 18
2.2.6 界面陷阱能態(Interface Trap State, Nit) 19
2.2.7 開啟(Ion)與關閉(Ioff)狀態之電流 19
第三章 結果與討論 28
3.1 Underlap電性與變溫現象 28
3.2 Underlap之效應 28
3.3 表面電漿處理後之現象 29
3.4 Underlap在電漿處理後之分析 30
第四章 結論 43
參考文獻 44
參考文獻 References
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